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71m6511/71m6511h single - phase energy meter ic data sheet november 20 10 page: 1 of 98 ? 2005 C 2010 teridian semiconductor corporation v2.7 a maxim integrated products brand general description the 71m6511 is a highly integrated soc with an mpu core, rtc, flash , and lcd driver. our single converter technology ? with a 22 - bit delta - sigma adc, three analog inputs, digital tempera ture compensa tion, precision voltage reference , and 32 - bit computation engine (ce) supports a wide range of single - phase metering applications with very few low cost external components. a 32khz crystal time base for the entire sys tem and internal battery backup support for ram and rtc further reduce sys tem cost. maximum design flexibility is supported with multiple uarts, i 2 c, a power fail comparator, a 5v lcd charge pump, up to 12 dio pins and an in - system programmable flash . the device is offered in high (0.1%) and standard (0.5%) accuracy versions for multi function re si dential/commercial meter applications requiring multiple voltage/current inputs and complex lcd or dio configurations. a complete array of ice and development tools, programming libraries an d reference designs enable rapid development and certification of mete rs that meet most demanding worldwide electricity metering standards. mpu rtc timers ia va ib xin xout vref rx tx v1 txrx com0..3 v3.3a v3.3d vbat v2.5 vlcd vbias vdrv seg0..19 gnda gndd seg 24..32 dio 0..11 seg 32..41 dio 12..21 ice load 88.88.8888 eeprom power fault ir amr test pulses battery comparator sense drive serial ports osc/pll converter lcd driver dio, pulse compute engine flash ram voltage ref regulator 5v boost power supply teridian 71m6511 3v/5v lcd temp sensor v or i 32 khz live neut ct/shunt 7/20/2007 features ? wh accuracy < 0.1% over 2000:1 range ? exceeds iec 62053 /ansic 12.20 ? voltage reference < 10ppm/ c -- 71m6511h, < 50ppm/c -- 71m6511 ? three sensor inputs - v dd referenced ? low jitter wh/varh pulse outputs ? pulse count for pulse outputs ? four - quadrant metering ? voltage/current angle ? line frequency count for rtc ? digital temperature compensation ? sag detection ? independent 32 - bit compute engine ? 40 - 70hz line frequency range with same calibration ? phase compensation ( 7 ) ? battery b ackup for ram and rtc ? 22mw at 3.3v, 7.2 w back up ? flash memory option with security ? 22 - bit delta - sigma adc ? 8- bit mpu (80515) - 1 clock cycle per instruction ? lcd driver ( 128 pixels) ? high speed ssi serial output ? rtc for time - of - use functions ? hardware watchdog timer ? up to 12 general - purpose i/o pins ? 64kb f lash, 7kb ram ? two uarts for ir and amr ? 64 - lead lqfp package 19 - 5359 ; rev 11/10 single converter technology is a registered trademark of maxim integrated products, inc. downloaded from: http:///
71m6511/71m6511h single - phase energy meter ic data sheet november 20 10 page: 2 of 98 ? 2005 C 2010 teridian semiconductor corporation v2.7 a maxim integrated products brand table of contents general description ................................................... ................................................... ............................... 1 features ................................................... ................................................... ....................................... 1 hardware description ................................................... ................................................... .......................... . 8 hardware overview ................................................... ................................................... ............................ 8 analog front end (afe) ................................................... ................................................... ..................... 8 multiplexer ................................................... ................................................... ............................ 8 adc ................................................... ................................................... ..................................... 9 fir filter ................................................... ................................................... .............................. 9 voltage reference ................................................... ................................................... ................ 9 temperature sensor ................................................... ................................................... ............. 10 functional description ................................................... ................................................... .......... 10 computation engine (ce) ................................................... ................................................... ................... 11 meter equations ................................................... ................................................... ................... 12 pulse generator ................................................... ................................................... ................... 12 real - time monitor ................................................... ................................................... ................ 13 ce functional overview ................................................... ................................................... ....... 13 80515 mpu core ................................................... ................................................... ............................... 15 80515 overview ................................................... ................................................... ................... 15 memory organization ................................................... ................................................... ........... 15 special function registers (sfrs) ................................................... ........................................... 17 spe cial function registers (generic 80515 sfrs) ................................................... ................... 18 special function registers specific to the 71m6511 ................................................... ................. 20 instruction set ................................................... ................................................... ...................... 21 uart ................................................... ................................................... ................................... 21 timers and counters ................................................... ................................................... ............ 24 wd timer (software watchdog timer) ................................................... ..................................... 26 interrupts ................................................... ................................................... .............................. 29 external interrupts ................................................... ................................................... ................ 32 interrupt priority level stru cture ................................................... ............................................... 34 interrupt sources and vectors ................................................... .................................................. 35 on - chip resources ................................................... ................................................... ............................ 37 d io ports ................................................... ................................................... ............................. 37 physical memory ................................................... ................................................... .................. 38 oscillator ................................................... ................................................... .............................. 39 real - time clock (rt c) ................................................... ................................................... ......... 40 lcd drivers ................................................... ................................................... ......................... 40 lcd voltage boost circuitry ................................................... ................................................... .. 41 uart (uart0) and optical port (uart1) ................................................... ................................ 41 hardware reset mechanisms ................................................... .................................................. 42 reset pin (resetz) ................................................... ................................................... ............. 42 hardware watchdog timer ................................................... ................................................... ... 42 crystal frequency monitor ................................................... ................................................... .... 42 v1 pin ................................................... ................................................... .................................. 42 i2c interface (eeprom) ................................................... ................................................... ...... 43 internal clocks and clock dividers ................................................... ........................................... 44 battery ................................................... ................................................... ................................. 44 internal voltages (vbias, vbat, v2p5) ................................................... ................................... 44 test ports ................................................... ................................................... ............................ 44 downloaded from: http:///
71m6511/71m6511h single - phase energy meter ic data sheet november 20 10 page: 3 of 98 ? 2005 C 2010 teridian semiconductor corporation v2.7 a maxim integrated products brand functional description ................................................... ................................................... ......................... 47 theory of operation ................................................... ................................................... .......................... . 47 system timing summary ................................................... ................................................... .................... 47 data flow ................................................... ................................................... .......................................... 50 ce/mpu communication ................................................... ................................................... .................... 50 fault, reset, power - up ................................................... ................................................... ...................... 51 battery operation ................................................... ................................................... ............................... 52 power save modes ................................................... ................................................... ............................ 52 temperature compensation ................................................... ................................................... ............... 53 chopping circuitry ................................................... ................................................... .............................. 53 internal/external pulse generation and pulse counting ................................................... .......................... 55 program security ................................................... ................................................... ............................... 56 firmware interface ................................................... ................................................... ................................ 57 i/o ram map C in numerical order ................................................... ................................................... .... 57 sfr map (sfrs specific to teridian 80515) C in numerical order ................................................... ..... 58 i/o ram (configuration ram) C alphabetical order ................................................... ................................ 59 ce program and environment ................................................... ................................................... ............ 65 ce program ................................................... ................................................... ......................... 65 formats ................................................... ................................................... ................................ 65 constants ................................................... ................................................... ............................. 65 environ ment ................................................... ................................................... ......................... 66 ce calculations ................................................... ................................................... .................... 66 ce ram locations ................................................... ................................................... ............................. 67 ce front end data (raw data) ................................................... ................................................ 67 ce status word ................................................... ................................................... .................... 67 ce transfer variables ................................................... ................................................... .......... 68 typica l performance data ................................................... ................................................... .................... 75 wh accuracy at room temperature ................................................... ................................................... ... 75 varh accuracy at room temperature ................................................... .................................................. 75 harmonic performance ................................................... ................................................... ....................... 76 meter accuracy over temperature (71m6511h) ................................................... ..................................... 76 application information ................................................... ................................................... ........................ 77 connection of sensors (ct, resistive shunt, rogowski coil) ................................................... ................. 77 distinction between 71m6511 and 71m6511h parts ................................................... ............................... 77 temperature compensation and mains frequency stabilization for the rtc .............................................. 78 external temperature compensation ................................................... ................................................... .. 79 temperature measurement ................................................... ................................................... ................ 79 connecting lcds ................................................... ................................................... ............................... 80 connecting i2c eeproms ................................................... ................................................... ................. 82 connecting 5v devices ................................................... ................................................... ...................... 82 optical interface ................................................... ................................................... ................................. 83 connecting v1 and reset pins ................................................... ................................................... ........... 83 flash programming ................................................... ................................................... ............................ 84 mpu firmware library ................................................... ................................................... ........................ 84 specifications ................................................... ................................................... ........................................... 85 electrical specifications ................................................... ................................................... ...................... 85 logic levels ................................................... ................................................... .................... 86 vref, vbias ................................................... ................................................... ....................... 88 crystal oscillator ................................................... ................................................... ...... 88 lcd boost ................................................... ................................................... ........................ 90 lcd drivers ................................................... ................................................... ..................... 90 rtc ................................................... ................................................... ..................................... 90 downloaded from: http:///
71m6511/71m6511h single - phase energy meter ic data sheet november 20 10 page: 4 of 98 ? 2005 C 2010 teridian semiconductor corporation v2.7 a maxim integrated products brand resetz ................................................... ................................................... ............................... 90 comparators ................................................... ................................................... ................. 90 ram and flash memory ................................................... ................................................... 91 flash memory timing ................................................... ................................................... .... 91 eeprom interface ................................................... ................................................... ......... 91 recommended external components ................................................... ................................................... . 91 packaging information ................................................... ................................................... ........................ 92 pinout (top view) ................................................... ................................................... ................. 93 pin descriptions ................................................... ................................................... ................... 94 i/o equivalent circuits: ................................................... ................................................... ......... 96 ordering information ................................................... ................................................... .............. 97 figures figure 1: ic functional block diagram .......................................................................................................................... 7 figure 2: general topology of a chopped amplifier ..................................................................................................... 10 figure 3: afe block diagram ...................................................................................................................................... 11 figure 4: samples in multiplexer cycle ....................................................................................................................... 13 figure 5: accumulation int erval .................................................................................................................................. 13 figure 6: memory map .............................................................................................................................................. 15 figure 7: interrupt structure ...................................................................................................................................... 36 figure 8: dio ports block diagram ............................................................................................................................. 37 figure 9: oscillator circuit ......................................................................................................................................... 40 figure 10: lcd voltage boost circuitry ....................................................................................................................... 41 figure 11: voltage range for v1 ................................................................................................................................ 43 figure 12: voltage. current, momentary and accumulated energy ................................................................................ 47 figure 13: timing relationship between adc mux, ce, and serial transfers ................................................................ 48 figure 14: rtm output format .................................................................................................................................. 49 figure 15: ssi timing, ( ssi_fpol = ssi_rdypol = 0) ............................................................................................ 49 figure 16: ssi timing, 16 - bit field example (external device delays srdy) ................................................................ . 49 figure 17: mpu/ce data flow .................................................................................................................................... 50 figure 18: mpu/ce communication (functional) ......................................................................................................... 51 figure 19: mpu/ce communication (processing s equence) ........................................................................................ 51 figure 20: timing diagram for voltages, current and operation modes afte r power - up ................................................. 52 figure 21: chop polarity w/ au tomatic chopping ........................................................................................................ 54 figure 22: sequence with alternate multiplexer cycles ................................................................................................ 54 figure 23: sequence with alternate multiplexer cycl es and controlled chopping ........................................................... 55 figure 24: wh accuracy, 0.3a - 200a/240v ................................................................................................................ 75 figure 25: varh accuracy for 0.3a to 200a/240v perform ance ................................................................................... 75 figure 27: meter accuracy over harmonics at 240v, 30a ............................................................................................ 76 figure 29: resistive voltage divider (left), current transforme r (right) ......................................................................... 77 figure 30: resistive shunt (left), rogowski coil (right) ............................................................................................... 77 figure 31: crystal frequency over temperature .......................................................................................................... 78 figure 32: crystal compensation ............................................................................................................................... 79 figure 33: connecting lcds ...................................................................................................................................... 80 figur e 34: lcd boost circuit ...................................................................................................................................... 81 figure 35: eeprom connection ................................................................................................................................ . 82 figure 36: interfacing rx to a 0 - 5v signal .................................................................................................................. 82 figure 37: connection for optical components ........................................................................................................... 83 figure 38: voltage divider for v1 ............................................................................................................................... 83 fi gure 39: external components for resetz .............................................................................................................. 84 downloaded from: http:///
71m6511/71m6511h single - phase energy meter ic data sheet november 20 10 page: 5 of 98 ? 2005 C 2010 teridian semiconductor corporation v2.7 a maxim integrated products brand tables table 1: inputs selected in regular and alternate multiplexer cycles .............................................................................. 8 table 2: channel control based on mux_div and fir_len ........................................................................................ 9 table 3: ce dram locations for adc results ............................................................................................................. 12 table 4: standard meter equations (inputs shown gray are scanned but not use d for calculation) .................................. 12 table 5: stretch memory cycle width ......................................................................................................................... 16 table 6: internal data memory map ........................................................................................................................... 17 table 7: special function registers locations ............................................................................................................. 17 table 8: special function registers reset values ........................................................................................................ 18 table 9: psw register flags ...................................................................................................................................... 19 table 10: psw bit functions ...................................................................................................................................... 19 table 11: port registers ............................................................................................................................................ 20 t able 12: special function registers .......................................................................................................................... 21 table 13: baud rate generation ................................................................................................................................ . 22 table 14: uart modes .............................................................................................................................................. 22 table 15: the s0con register ................................................................................................................................... 22 table 16: the s1con register .................................................................................................................................... 23 table 17: the s0con bit functio ns ............................................................................................................................ 23 table 18: the s1con bit functions ............................................................................................................................ 24 table 19: the tmod register .................................................................................................................................... 24 table 20: tmod register bit description .................................................................................................................... 25 table 21: timers/counters mode description ............................................................................................................. 25 table 22: the tcon register ..................................................................................................................................... 25 table 23: the tcon register bit functions ................................................................................................................. 26 table 24: timer modes .............................................................................................................................................. 26 table 25: the pcon register ..................................................................................................................................... 26 table 26: the ien0 register (see also table 34) ......................................................................................................... 27 table 27: the ien0 bit functions (see also table 34) ................................................................................................... 27 table 28: the ien1 register (see also tables 35/36) ................................................................................................... 27 table 29: the ien1 bit functions (see also tables 35/36 ) ............................................................................................ 27 table 30: the ip0 register (see also table 46) ............................................................................................................ 28 table 31: the ip0 bit functions (see also table 46) ..................................................................................................... 28 table 32: the wdtrel register ................................................................................................................................ 28 table 33: the wdtrel bit functions ......................................................................................................................... 28 table 34: t he ien0 register ...................................................................................................................................... 29 table 35: the ien0 bit functions ............................................................................................................................... 30 table 36: the ien1 register ...................................................................................................................................... 31 table 37: the ien1 bit functions ............................................................................................................................... 31 table 38: the ien2 register ...................................................................................................................................... 31 table 39: the ien2 bit functions ............................................................................................................................... 31 table 40: the tcon register ..................................................................................................................................... 32 table 41: the tcon bit functions .............................................................................................................................. 32 table 42: the ircon register .................................................................................................................................... 32 table 43: the ircon bit functions ............................................................................................................................. 32 table 44: external mpu interrupts ............................................................................................................................. 33 table 45: control bits for external interrupts .............................................................................................................. 33 table 46: priority level groups .................................................................................................................................. 34 table 47: the ip0 register: ........................................................................................................................................ 34 table 48: the ip1 register: ........................................................................................................................................ 34 downloaded from: http:///
71m6511/71m6511h single - phase energy meter ic data sheet november 20 10 page: 6 of 98 ? 2005 C 2010 teridian semiconductor corporation v2.7 a maxim integrated products brand table 49: priority levels ............................................................................................................................................ 34 table 50: interrupt polling sequence .......................................................................................................................... 35 table 51: interrupt vectors ........................................................................................................................................ 35 table 52: data/direction registers and internal resources for dio pin groups ............................................................. 37 table 53: dio_dir control bit .................................................................................................................................. 38 table 54: selectable controls using the dio_d ir bits ................................................................................................ 38 table 55: mpu data memory map .............................................................................................................................. 38 table 56: liquid crystal display segment table (typical) ............................................................................................ 41 table 57: eectrl status bits ................................................................................................................................... 44 table 58: tmux[3:0] selections ............................................................................................................................... 45 table 59: ssi pin assi gnment .................................................................................................................................... 46 table 60: power saving measures ............................................................................................................................. 52 table 61: chop_en bits .......................................................................................................................................... 53 table 62: frequency over temperature ....................................................................................................................... 78 downloaded from: http:///
71m6511/71m6511h single - phase energy meter ic data sheet november 20 10 page: 7 of 98 ? 2005 C 2010 teridian semiconductor corporation v2.7 a maxim integrated products brand ia va ib mux xin xout vref cktest ce 32-bit compute engine mpu (8051) ce control opt_rx opt_tx resetz vbias v1 emulator port ce_busy optical uart tx rx xfer busy ce prog ram (4kb) com0..3 lcd display driver rtc data 00-ff prog 000-7ff data 0000-ffff prog 0000-ffff 0000-ffff mpu xram (2kb) 0000-07ff digital i/o config ram 2000-20ff i/o ram ce ram (1kb) memory share 3000-3fff 1000-13ff rtclk rtclk (32khz) mux_sync ckce ckmpu ce_run ce_load ce_en rtm_en comp_int comp_stat power fault lcd_en lcd_clk lcd_mode dio_gp rtc_set < 4.9mhz 4.9 mhz gndd v3p3a v3p3d vbat volt reg 2.5v to logic 0.1v v2p5 mpu_div sum_cycles pre_samps equ ckout_en vlcd tmuxout faultz wake vbias dmux tmux configuration parameters vdrv gnda vbias temp october 5, 2005 ck_gen osc (32khz) osc_dis ck32 ck_en mck pll voltage boost lcd_bsten lcd_ibst vref vref_dis mux ctrl mux_div chop_en equ strt mux mux ckfir 4.9 mhz mux_sync rtm rtm seg34/dio14 ... seg37/dio17 gnda wpulse varpulse wpulse varpulse test gndd < 4.9mhz lcd_num dio_out dio_in lcd_num rtc_hold 0 1 2 3 4 5 6 7 8 9 a b c d e f dgnd ibias wdtr_en reserved reserved optrx analog digital pulsev/w mux_alt seg24/dio4 ... seg31/dio11 ckmpu_2x scl sda flash (64kb) eewrslow eerdslow v3p3a fir_len fir filter ck_10m ck_mpu reserved seg0..seg2 eeprom interface dio_eex pll_2.5v ck_2x eck_dis opt_txdis ? adc converter + - vref rtclk ce_busy xfer_busy vbias v3p3 v2p5 seg3/sclk seg4/ssdata seg5/sfr seg6/srdy seg7/ mux_sync seg8..seg19 ssi figure 1 : ic functional block diagram downloaded from: http:///
71m6511/71m6511h single - phase energy meter ic data sheet november 20 10 page: 8 of 98 ? 2005 C 2010 teridian semiconductor corporation v2.7 a maxim integrated products brand hardware description hardware overview the teridian 71m6511 single chip single - phase meter integrates all primary functional blocks required to impl ement a solid - state electricity meter. included on chip are an analog front end (afe), an 8051 - compatible microprocessor (mpu) which executes one instruction per clock cycle (80515), an independent 32 - bit digital co mputation engine (ce), a voltage reference, a temperature sensor, lcd drivers, ram, flash memory, a real time clock (rtc), and a variety of i/o pins. var ious current sensor technologies are supported including current transformers (c t), resistive shun ts, and rogowski ( di/dt) coils. in addition to advanced measurement functions, the real time clock function allows t he 71m6511/6511h to record time of use (tou) metering information for multi - rate applications. measurements can be displayed on either a 3v or a 5v lcd. flexible mapping of lcd display segments will facilitate integration with any lcd forma t. the design trade - off between the number of lcd segments and dio pins can be flexibly configured using memory - mapped i/o to accommodate various requireme nts. the 71m6511 includes several i/o peripheral functions that improve the functionality of the device and reduce the component count for most meter applications. the i/o peripherals include two ua rts, digital i/o, comparator inputs, lcd display drivers , i 2 c interface and an optical/ir interface. one of the two internal uarts (uart1) is adapted to support an infrar ed led with internal drive output and sense input but it can also function as a standard uart. a block diagram of the chip is shown in figure 1 . a detailed description of various hardware blocks follows. analog front end (afe) the afe of the teridian 71m6511 power meter ic is comprised of an input multiplex er, a delta - sigma a/d converter with a voltage reference, followe d by an fir filter. a block diagram of the afe is shown in figure 3. multiplexer the input multiplexer supports four input signals that are applied to the pins ia, va, and i b plus the output of the internal temperature sensor. the multiplexer can be operated in two modes: ? during a normal multiplexer cycle, the signals from the pins ia, va, and ib, are selected. ? during the alternate multiplexer cycle, the temperature signal (temp) is selected, along with the other signal sources sho wn in table 1. alternate multiplexer cycles are usually performed infrequently (every secon d or so). va is not replaced in the alternate mul ti - plexer cycles. missing samples due to alternate multiplexer cycles are automatically in ter polated by the ce. equ channels used from mux sequence states 0 3 channels used from alternative mux sequence states 0 3 0 1 2 3 0 1 2 3 000 ia va ib - temp va - - 001 ia va ib - temp va ib - table 1 : inputs selected i n regular and alternate multiplexer cycles in a typical application, the ia input is connected to a current transformer that senses the line current. va is typically co n nected to a voltage sensor through resistor dividers. ib may be connect ed to a second current transformer, e.g. for optional tamper detection. the multiplexer control circuit handles the setting of the multi plexer. the function of the multiplexer control circuit is governed by the i/o ram registers mux_alt (0x2005[2]), equ (0x2000[7:5]), a nd mux_div (0x2002[7:6]). mux_div controls the number of samples per cycle. it can request 2, 3, 4, or 6 mul tiplexer states per cycle. downloaded from: http:///
71m6511/71m6511h single - phase energy meter ic data sheet november 20 10 page: 9 of 98 ? 2005 C 2010 teridian semiconductor corporation v2.7 a maxim integrated products brand the mux_alt bit requests an alternate multiplexer cycle. the bit may be asserted on any mpu cycle and may be sub - sequentl y de - asserted on any cycle including the next one. a rising edge on mux_alt will cause the control circuit to wait until the next multiplexer cycle and implement a single alternate cycle. multiplexer control circuit also controls the fir filter initiation and the chopping of the adc reference voltage, vref. t he multiplexer control circuit is clocked by ck32, the 32768hz clock from the pll block, and launches each pass through the ce program. table 2 shows the possible settings for mux_div and fir_len and the resulting channels sampled along with sample frequencies. mux_div (0x2002[7.6]) number of channels selected (mux states per cycle) number of ck32 states for code pass effective sample frequency [hz] number of ck32 states for c ode pass effective sample frequency [hz] fir_len = 0 fir_len =1 00 --- not allowed 01 4 9 3640.89 13 2520.615 10 3 7 4681.143 10 3276.8 11 2 5 6553.6 7 4681.143 table 2 : channel control based on mux_div and fir_len adc a sin gle 21/22 - bit delta - sigma a/d converter (adc) digitizes the power inputs to the afe. the resolu tion of the adc is programmable using the i/o ram register fir_len register (0x2005[4]). adc resolution may be selected to be 21 bits ( fir_len =0), or 22 bits ( fi r_len =1). con version time is two cycles of ck32 with fir_len = 0 and three cycles with fir_len = 1. in order to provide the maximum resolution, the adc should be operated with fir_len = 1. accuracy, timing and functional specifications in this data sheet are based on fir_len = 1 and mux_div = 1 (four ck32 cycles). alterna tive specifications are also provided for fir_len = 1 and mux_div = 2 (three ck32 cycles) in the ce program and environment section. initiation of each adc conversion is controlled by the multiplexer control circuit as described previously. fir filter the finite impulse response (fir) filter is an integral part of the adc an d it is optimized for use with the multiplexer. the purpose of the fir is to decimate the adc output to the desired reso lution. at the end of each adc conversion, the output data of the fir filter (raw data) is stored into the ce dram location det ermined by the multiplexer selection. the location o f the raw data in the ce dram is specified in the ce program and e nvironm ent section. voltage reference the 71m6511/6511h includes an on - chip precision bandgap voltage reference that incorporates auto - zero techniques. the reference of the 71m6511h is trimmed in production to minimize error s caused by component mismatch and drif t. the result is a voltage output with a predictable temperature coefficient. the voltage reference is chopper stabilized, i.e. the polarity can be switched by the mpu using the i/o ram register chop_ena (0x2002[5:4]). the two bits in the chop_ena registe r enable the mpu to operate the chopper circuit in regular or inverted operation, or in toggling mode. when the chopper circuit is t oggled in between multiplexer cycles, dc offsets on t he measured signals will automatically be averaged out. the general topology of a chopped amplifier is given in figure 2 . downloaded from: http:///
71m6511/71m6511h single - phase energy meter ic data sheet november 20 10 page: 10 of 98 ? 2005 C 2010 teridian semiconductor corporation v2.7 a maxim integrated products brand g - + v inp v outp v outn v inn cross ab ab a b a b figure 2 : general topology of a chopped amplifier it is assumed that an offset voltage voff appears at the positive amplifier input. with all switches, as controlled by cross in the a position, the output voltage is: voutp C voutn = g (vinp + voff C vinn) = g (vinp C vinn) + g voff with all switches set to the b position by applying the invert ed cross signal, the output voltage is: voutn C voutp = g (vinn C vinp + voff) = g (vinn C vinp) + g voff, or voutp C voutn = g (vinp C vinn) - g voff thus, when cross is toggled, e.g. after each multiplexer cycle, t he offset will alternately appear on the output as positive and negative, which results in the offset effectively being eliminated, regardless of its polarity or m agnitude. the functional description section contains a chapter with a detai led description on controlling the chop_ena register. temperature sensor the 71m6511/6511h includes an on - chip t emperature sensor implemented as a bandgap reference. it is used to determine the die temperature the mpu may request an alternate multiplexer cycle containing the temperature sensor output by asserting mux_alt . the primary use of the temperature data is to determine the magnitude of compensation requi red to offset the thermal drift in the system (see section titled temperature compensation). the zero reference for the temperature sensor is vbias. functional description the afe functions as a data acquisition system, controlled by the mpu. the main signals (ia, va, ib) are sampled and the adc counts obtained are stored in ce ram where they can be accessed by the ce and, if ne cessary, by the mpu. alternate multiplexer cycles are initiated less frequently by the mpu to gather access to the slow temperature signal. ia va ib mux vref vbias vbias temp ck32 vref vref_dis mux ctrl mux_div chop_en equ mux mux_alt v3p3a fir_len fir filter ? adc converter + - vref downloaded from: http:///
71m6511/71m6511h single - phase energy meter ic data sheet november 20 10 page: 11 of 98 ? 2005 C 2010 teridian semiconductor corporation v2.7 a maxim integrated products brand figure 3 : afe block diagram computation engine (ce) the ce, a dedicated 32 - bit risc processor, performs the precision computations necessary to accurately measure energy. the ce calculations and processes include: ? multiplication of each current sample with its associated voltage sample t o obtain the energy per sample (when multiplied with the constant sample time). ? frequency - insensitive delay cancellation on all six channels (to compensate for the delay betwee n samples caused by the multiplexing scheme). ? 90 phase shifter (for var calculations). ? pulse generation. ? monitoring of the input signal frequency (for frequency and phase inform ation). ? monitoring of the input signal amplitude (for sag detection). ? scaling of the processed samples based on chip temperature (temperature c ompensation) and calibration coefficients. the ce program ram (ce pram) is loaded at boot time by the mpu and then executed by the ce. each ce instruction word is 2 bytes long. the ce program counter begins a pass through the ce code each time multiplexer state 0 begins. the code pass ends when a halt instruction is executed. for proper operation, the code pass must be completed before the multiplexer cycle ends (see system timing summary in the functio nal description section). the ce data ram (ce dram) can be accessed by the fir filter block, the rtm circuit, the ce, and the mpu. assigned time slots are reserved for fir, rtm, and mpu, respectively, such t hat memory accesses to ce_ram do not collide. holding re - gisters are used to convert 8 - bit wide mpu data to/from 32 - bit wide ce dram data, and wait states are inserted as needed, depending on the frequency of ckmpu. table 3 shows the ce dram addresses allocated to analog inputs from the afe. downloaded from: http:///
71m6511/71m6511h single - phase energy meter ic data sheet november 20 10 page: 12 of 98 ? 2005 C 2010 teridian semiconductor corporation v2.7 a maxim integrated products brand address (hex) name description 0x00 ia phase a current 0x01 va phase a voltage 0x02 ib phase b current 0x03 - reserved 0x04 - reserved 0x05 - reserved 0x06 temp temperature 0x07 -- re served table 3 : ce dram locations for adc results meter equations the compute engine (ce) program for residential meter configurations imp lements the equations in table 4 . the i/o ram register equ specifie s the equation to be used based on the number and arrangement of phases used for metering. in case of single - phase metering, the unconnected input should be tied to v3p3a, the analog suppl y voltage. the equ selection enables the 71m6511 to calculate single - phase power measurement based on the type of service used. table 4 also states the sequence of the multiplexer in the afe. equ formula channels used from mux sequence states 0 3 channels used from alternative mux sequence stat es 0 3 0 1 2 3 0 1 2 3 000 va ia (1 element, 2w 1 ) ia va ib - temp va - - 001 va(ia - ib)/2 (1 element, 3w 1 ) ia va ib - temp va ib - table 4 : standard meter equations (inputs shown gray are scanned but not us ed for calculat ion) pulse generator the ce contains two pulse generators which create low jitter pulses at a rate set by the ce dram registers apulsew*wrate and apulser * wrate if ext_pulse (a ce input variable in ce dram) is 15. this mode puts the mpu in control of puls e generation by placing values into the apulsew and apulser registers (external pulse generation). if ext_pulse is 0, apulsew is replaced with wsum_x and apulser is replaced with varsum_x . in this mode, the ce generates pulse based on its internal computa tion of wsum_x and varsum_x , the signed sums of energy from all three elements (internal pulse generation). the dio_pv and dio_pw bits as described in the digital i/o section can be programmed to route wpulse and var pulse to the output pins dio6 and dio7 respectively. dio6 and dio7 can be configured to generate interrupts (useful fo r pulse counting by the mpu C see on - chip resources (dio section). downloaded from: http:///
71m6511/71m6511h single - phase energy meter ic data sheet november 20 10 page: 13 of 98 ? 2005 C 2010 teridian semiconductor corporation v2.7 a maxim integrated products brand real - time monitor the ce contains a real time monitor (rtm), which can be programmed to monitor four se lect able ce ram locations at full sample rate. the four monitored locations are serially output to the tmux out pin via the digital output multiplexer at the beginning of each ce code pass (s ee the test ports section for details) ce functional overview the adc processes one sample per channel per multiplexer cycle. figure 4 shows the timing of the samples taken during one multiplexer cycle. the number of samples processed during one accumulation cycle is controlled by the i/o ram regist ers pre_samps (0x2001[7:6]) and sum_cycles (0x2001[5:0]). the integration time for each energy output is pre_samps * sum_cycles / 2520.6, where 2520.6 is the sample rate [hz] (for mux_div = 1) for example, pre_samps = 42 and sum_cycles = 50 will establish 2100 samples per accumulation cycle. pre_samps = 100 and sum_cycles = 21 will result in the exact same accumulation cycle of 2100 samples or 833ms. a fter an accumulation cycle is completed, the xfer_busy interrupt signals to the m pu that accumulated data are available. va ia 1/32768hz = 30.518s 13/32768hz = 397s per mux cycle ib va ia 1/32768hz = 30.518s 13/32768hz = 397s per mux cycle ib figure 4 : samples in multiplexer cycle the end of each multiplexer cycle is signaled to the mpu by the ce_busy interru pt. at the end of each multiplexer cycle, status information, such as sag data and the digitized input signal, is available to the mpu. xfer_busy interrupt to mpu 20ms 833ms xfer_busy interrupt to mpu 20ms 833ms figure 5 : accumulation interval figure 5 shows the accumulation interval resulting from mux_div = 1, pre_samps = 42 and sum_cycles = 50, con sisting of 2100 samples of 397s each, followed by the xfer_busy interrupt. the s ampling in this example is applied to a 50hz signal. downloaded from: http:///
71m6511/71m6511h single - phase energy meter ic data sheet november 20 10 page: 14 of 98 ? 2005 C 2010 teridian semiconductor corporation v2.7 a maxim integrated products brand there is no correlation between the line signal frequency and the choice of pre_samps or sum_cycles ( even though when sum_cycles = 42 one set of sum_cycles happens to sample a period of 16.6ms). furthermore, sampling does not have to start when the line voltage crosses the zero line. delay compensation when measuring the energy of a phase (i.e., wh and varh) in a service, the voltage and curre nt for that phase must be sampled at the same instant. otherwise, the phase difference, , in troduces errors. o delay o delay f t t t 360 360 ? ? = ? = where f is the frequency of the input signal and t delay is the sampling delay between voltage and current. in tradition al met er ics, sampling is accomplished by using two a/d converters per phase (one f or voltage and the other one for current) controlled to sample simultaneously. teridians single - converter technology ? , however, ex ploits the 32 - bit signal processing capability of its ce to implement constant delay all - pass filters. these all - pass filters correct for the conversion time difference between the voltage and the corresponding current samp les that are obtained with a single multiplexed a/d converter. the constant delay all - pass filters provide a broad - band delay that is precisely matched to the differ ence in sample time between the voltage and the current of a given phase. this digital fil ter does not affect the amplitude of the signal, but provides a precisely controlled phase response. the delay compensation implemented in the ce aligns the voltage samples with their corresponding current samples by routing the voltage samples through the all - pass filter, thus delaying the voltage samples by , resu lting in the residual phase error C . the residual phase error is negligible, and is typically less t han 1.5 milli - degrees at 100hz, thus it does not contribute to errors in the energy measur ements. downloaded from: http:///
71m6511/71m6511h single - phase energy meter ic data sheet november 20 10 page: 15 of 98 ? 2005 C 2010 teridian semiconductor corporation v2.7 a maxim integrated products brand 80515 mpu core 80515 overview the 71m6511/6511h includes an 80515 mpu (8 - bit, 8051 - compatible) that processes most instructions in one clock cycle. using a 5mhz clock results in a processing throughput of 5 mips. the 80515 architecture elim inates redundant bus states and im plements parallel execution of fetch and execution phases. normally a machine cycle is aligned with a memory fetch, there - fore, most of the 1 - byte instructions are performed in a single cycle. this leads to an 8x performance ( in average) improvement (in terms of mips) over the intel 80 51 device running at the same clock frequency . actual processor clocking speed can be adjusted to the total processing demand of the appl ication (metering calculations, amr management, memory management, lcd driver management and i/o manageme nt) using the i/o ram register mpu_div[2:0] . typical measurement and metering functions based on the results provided by the internal 32 - bit compute engine (ce) are available for the mpu as part of teridians standard library. a standard ansi c 80515 - application prog ramming interface library is available to help reduce design cycle. memory organization the 80515 mpu core incorporates the harvard architecture with separ ate code and data spaces. memory organization in the 80515 is similar to that of the industry standar d 8051. there are three memory areas: program memory ( f lash), external data memory (xram), physically consisting of xra m, ce dram, ce pram and i/o ram, and internal data memory (internal ram). figure 6 shows the memory map (see a lso table 55 ). internal and external data memory: both internal and external data memory are physically located on the 71m6511 ic. ex - ternal data memory is only external to the 80515 mpu core. 0xffff flash memory 0xffff --- 0x4000 0x3fff ce pram 0x3000 0x2fff --- 0x2100 0x20ff i/o ram 0x2000 0x1fff --- 0x1400 0x13ff ce dram 0x1000 0x0fff --- 0x0800 0x07ff xram 0xff sfrs, ram, reg. banks 0x0000 0x0000 0x00 program memory external data memory internal data memory figure 6 : memory map program memory: the 80515 can address up to 64kb of program memory space from 0x0000 to 0xffff. program memory i s read when the mpu fetches instructions or performs a movc oper ation. after reset, the mpu starts program execution from location 0x00 00. the lower part of the program memory includes reset and interrupt vectors. the interrupt vectors are spaced at 8 - byte intervals, starting from 0x0003. external data memory: while the 80515 can address up to 64kb of external data memory in the space from 0x0000 to 0xffff, only the memory ranges shown in figure 6 contain physical memory. the 80515 writes into external data memory downloaded from: http:///
71m6511/71m6511h single - phase energy meter ic data sheet november 20 10 page: 16 of 98 ? 2005 C 2010 teridian semiconductor corporation v2.7 a maxim integrated products brand when the mpu executes a movx @ri,a or movx @dptr,a instruct ion. the mpu reads external data memory by executing a movx a,@ri or movx a,@dptr instruction (sfr usr2 provides the upper 8 bytes for the movx a,@ri instruction) . clock stretching: movx instructions can access fast or slow external ram and external peripherals . the three low ordered bits of the ckcon register define the stretch memory cycles. setting all the ckcon stretch bits to one allows access to very slow ext ernal ram or external peripherals. table 5 shows how the signals of the external memory interface change when stretch values are set from 0 to 7. the widths of the signals are counted in mpu clock cycles. the post - reset state of t he ckcon register, which is in bold in the table, performs the movx instructions with a stretch value equal to 1. ckcon register stretch value read signals width write signal width ckcon.2 ckcon. 1 ckcon. 0 memaddr memrd memaddr memwr 0 0 0 0 1 1 2 1 0 0 1 1 2 2 3 1 0 1 0 2 3 3 4 2 0 1 1 3 4 4 5 3 1 0 0 4 5 5 6 4 1 0 1 5 6 6 7 5 1 1 0 6 7 7 8 6 1 1 1 7 8 8 9 7 table 5 : stretch memory cycle width there are two types of instructions, differing in whether they provide an eight - bit or sixteen - bit indirect address to the external data ram. in the first type (movx a,@ri), the contents of r0 or r1, in the current registe r bank, provide the eight lower - ordered bits of address. the eight high - ordered bits of address are specified with the usr2 sfr. this method allows the user paged access (256 pages of 256 bytes each) to the full 64kb of external data ram. in the second type of movx i nstruction (movx a,@dptr), the data pointer generates a sixteen - bit address. this form is faster and more efficient when acces sing very large data arrays (up to 64 kbytes), since no additional instructions are ne eded to set up the eight high ordered bits of address. it is possible to mix the two movx types. this provides the user with f our separate data pointers, two with direct access and two with paged access to the entire 64kb of external memory range . dual data pointer: the dual data pointer accelerates the block moves of data. the s tandard dptr is a 16 - bit register that is used to address external memory or peripherals. in the 80515 core, t he standard data pointer is called dptr, the second data pointer is called dptr1. the data pointer select bit chooses the active pointer. the data poi nter select bit is located at th e lsb of the dps register (dps.0). d ptr is selected when dps.0 = 0 and dptr1 is selected when dps. 0 = 1. the user switches between pointers by toggling the lsb of the dps register. all dp tr - related instructions use the currently selected dptr for any activity. the second data pointer may not be supported by certain compilers. downloaded from: http:///
71m6511/71m6511h single - phase energy meter ic data sheet november 20 10 page: 17 of 98 ? 2005 C 2010 teridian semiconductor corporation v2.7 a maxim integrated products brand internal data memory: the internal data memory provides 256 bytes (0x00 to 0xff) of data mem ory. the internal data memory address is always 1 byte wide and can be accessed by either direct or indirect addressing. the special function registers occupy the upper 128 bytes . this sfr area is available only by direct addressing. indirect addr essing accesses the upper 128 bytes of internal ram. the lower 128 bytes contain working registers and bit - addressable memory. the lower 32 bytes form four banks of eight registers (r0 - r7). two bits on the program memory status word (psw) select which bank is i n use. the next 16 bytes form a block of bit - addressable memory space at bit addressees 0x00 - 0x7f. all of the bytes in the lower 12 8 bytes are accessible through direct or indirect addressing. table 6 shows the internal data memory map. address direct addressing indirect addressing 0xff special function registers (sfrs) ram 0x80 0x7f byte - addressable are a 0x30 0x2f bit - addressable area 0x20 0x1f register banks r0r7 0x00 table 6 : internal data memory map special function registers (sfrs) a map of the special function registers is shown in table 7. hex \ bi n bit - address - able byte - addressable bin/he x x000 x001 x010 x011 x100 x101 x110 x111 f8 intbits ff f0 b f7 e8 wdi ef e0 a e7 d8 wdcon df d0 psw d7 c8 cf c0 ircon c7 b8 ien1 ip1 s0re lh s1relh usr2 bf b0 flshctl pgadr b7 a8 ien0 ip0 s0rell af a0 p2 dir2 dir0 a7 98 s0con s0buf ien2 s1con s1buf s1rell eedata eectrl 9f 90 p1 dir1 dps erase 97 88 tcon tmod tl0 tl1 th0 th1 ckcon 8f 80 p0 sp dpl dph dpl1 dph1 w dtrel pcon 87 table 7 : special function registers locations only a few addresses are occupied, the others are not implemented. sfrs specific t o the 651x are shown in bold print. any read access to unimplemented addresses will return undefined data, while any write acc ess will have no effect. the registers at 0x80, 0x88, 0x90, etc., are bit - addressable, all others are byte - addressable. downloaded from: http:///
71m6511/71m6511h single - phase energy meter ic data sheet november 20 10 page: 18 of 98 ? 2005 C 2010 teridian semiconductor corporation v2.7 a maxim integrated products brand special function registers (generic 80515 sfrs) table 8 shows the locati on of the sfrs and the value they assume at reset or power - up. name location reset value description p0 0x80 0xff port 0 sp 0x81 0x07 stack pointer dpl 0x82 0x00 data pointer low 0 dph 0x83 0x00 data pointer high 0 dpl1 0x84 0x00 data pointer low 1 dph1 0x85 0x00 data pointer high 1 wdtrel 0x86 0x00 watchdog timer reload register pcon 0x87 0x00 uart speed control tcon 0x88 0x00 timer/counter control tmod 0x89 0x00 timer mode control tl0 0x8a 0x00 timer 0, low byte tl1 0x8b 0x00 timer 1, high byte th0 0x8c 0x00 timer 0, low byte th1 0x8d 0x00 timer 1, high byte ckcon 0x8e 0x01 clock control (stretch=1) p1 0x90 0xff port 1 dps 0x92 0x00 data pointer select register s0con 0x98 0x00 serial port 0, control register s0buf 0x99 0x00 serial port 0, data buffer ien2 0x9a 0x00 interrupt enable register 2 s1con 0x9b 0x00 serial port 1, control register s1buf 0x9c 0x00 serial port 1, data buffer s1rell 0x9d 0x00 serial port 1, reload register, low byte p2 0xa0 0x00 port 2 ien0 0xa8 0x00 interrupt enable register 0 ip0 0xa9 0x00 interrupt priority register 0 s0rell 0xaa 0xd9 serial port 0, reload register, low byte p3 0xb0 0xff port 3 ien1 0xb8 0x00 interrupt enable register 1 ip1 0xb9 0x00 interrupt priority regi ster 1 s0relh 0xba 0x03 serial port 0, reload register, high byte s1relh 0xbb 0x03 serial port 1, reload register, high byte usr2 0xbf 0x00 user 2 port, high address byte for movx@ri ircon 0xc0 0x00 interrupt request control register psw 0xd0 0x00 program status word wdcon 0xd8 0x00 baud rate control register (only wdcon .7 bit used) a 0xe0 0x00 accumulator b 0xf0 0x00 b register table 8 : special function registers reset values downloaded from: http:///
71m6511/71m6511h single - phase energy meter ic data sheet november 20 10 page: 19 of 98 ? 2005 C 2010 teridian semiconductor corporation v2.7 a maxim integrated products brand accumulator ( acc, a ): acc is the accumu lator register. most instructions use the accumulator to hold the operand. the mnemonics for accumulator - specific instructions refer to accumulator as a, not acc . b register: the b register is used during multiply and divide instructions. it can also be used as a scratch - pad register to hold temporary data. program status word ( psw ): msb lsb cv ac f0 rs1 rs ov - p table 9 : psw register flags bit symbol function psw.7 cv carry flag psw.6 ac auxiliary carry flag for bcd operation s psw.5 f0 general purpose flag 0 available for user. not to be confused with the f0 flag in the ce status register. psw.4 rs1 register bank select control bits. the contents of rs1 and rs0 select the working register bank: rs1/rs0 bank selected location 00 bank 0 (0x00 C 0x07) 01 bank 1 (0x08 C 0x0f) 10 bank 2 (0x10 C 0x17) 11 bank 3 (0x18 C 0x1f) psw.3 rs0 psw.2 ov overflow flag psw.1 - user defined flag psw.0 p parity flag, affected by hardware to indicate odd / even number of one bits in the accumulator, i.e. even parity. table 10 : psw bit functions stack pointer ( sp ): the stack pointer is a 1 - byte register initialized to 0x07 after reset. this register is incremen ted before push and call instructions, causing the stack to begin at location 0x08. data pointer: the data pointer ( dptr ) is 2 bytes wide. the lower part is dpl , and the highest is dph . it can be loaded as a 2 - byte register (mov dptr,#data16) or as two registers (e.g. m ov dpl,#data8). it is generally used to access external code or data space (e.g. movc a,@a+dptr or movx a,@dptr respectiv ely). program counter: the program counter ( pc ) is 2 bytes wide initialized to 0x0000 after reset. this register is increm ented during the fetching operation code or when operating on data from program memory. downloaded from: http:///
71m6511/71m6511h single - phase energy meter ic data sheet november 20 10 page: 20 of 98 ? 2005 C 2010 teridian semiconductor corporation v2.7 a maxim integrated products brand port registers: the i/o ports are controlled by special function registers p0 , p1 , and p2 . the contents of the sfr can be observed on corresponding pins on the chip. writing a 1 to any of the ports (see table 11 ) causes the corresponding pin to be at high level (v3p3), and writing a 0 causes the corresponding pin to be held at low level (gnd ). the data direction registers dir0 , dir1 , and dir2 define individual pins as input or output pins (see section on - chip resources C dio ports for details). register sfr addres s r/w description p0 0x80 r/w register for port 0 read and write operations (pins dio4dio7) dir0 0xa2 r/w data direction register for port 0. setting a bit to 1 means that the corresponding pin is an output. p1 0x90 r/w register for port 1 read and write operations (pins dio8dio1 5) dir1 0x91 r/w data direction register for port 1. p2 0xa0 r/w register for port 2 read and write operations (pins dio16 - dio17) dir2 0xa1 r/w data direction register for port 2. table 11 : port registers all four ports on the chip are bi - directional. each of them consists of a latch (sfr p0 to p3 ), an output driver, and an input buffer, therefore the m pu can output or read data through any of these ports. even if a dio pi n is configured as an output, the state of the pin can still be read by the mpu, for example whe n counting pulses issued via dio pins that are under ce control . special function registers specific to the 71m6511 table 12 shows the location and description of the 71m6511 - specific sfrs. register alternative name sfr addres s r/w description erase flsh_erase 0x94 w this register is used to initiate either the flash mass erase cycle or the flash page erase cycle. specific patterns are expected for flsh_erase in order to initiate the appropriate erase cycle (default = 0x00). 0x55 C initiate flash page erase cycle. must be proceeded by a write to flsh_pgadr @ sfr 0xb7. 0xaa C initiate flash mass erase cycle. must be proceeded by a write to flsh_meen @ sfr 0xb2 and the debug port must be enabled. any other pattern written to flsh_erase will have no effect. pgaddr flsh_pgadr 0xb7 r/w flash page erase address register con taining the flash memory page address (page 0 thru 127) that will be erased during the page erase cycle (default = 0x00). must be re - written for each new page erase cycle. eedata 0x9e r/w i2c eeprom interface data register eectrl 0x9f r/w i2c eeprom in terface control register. if the mpu wishes to write a byte of data to eeprom, it places the data in eedata and then writes the transmit code to eectrl . the write to eectrl initiates the transmit sequence. see the section i2c interface (eeprom) for a description of the command and status bits available for eectrl . downloaded from: http:///
71m6511/71m6511h single - phase energy meter ic data sheet november 20 10 page: 21 of 98 ? 2005 C 2010 teridian semiconductor corporation v2.7 a maxim integrated products brand flshcrl 0xb2 r/w w r/w r bit 0 ( flsh_pwe ): program write enable: 0 C movx commands refer to xram space, normal operation (default). 1 C movx @dptr,a moves a to program space ( f lash) @ dptr. this bit is automatically reset after each byte written to fla sh. writes to this bit are inhibited when interrupts are enabled. bit 1 ( flsh_meen ): mass erase enable: 0 C mass erase disable d (default). 1 C mass erase enabled. must be re - written for each new mass erase cycle. bit 6 ( secure ): enables security provisions that prevent external reading of flash memory and ce program ram. this bit is reset on chip reset and may only be set. attempts to write zero are ignored. bit 7 ( preboot ): indicates that the preboot sequence is active. wdi 0xe8 r/w r/w w only byte operations on the whole wdi register should be used when writing . the byte must have all bits set except the bits that are to be cleared. the multi - purpose register wdi contains the following bits: bit 0 ( ie_xfer ): xfer interrupt flag: this flag mo nitors the xfer_busy interrupt. it is set by hardware and must be cleared by the in terrupt handler bit 1 ( ie_rtc ): rtc inter rupt flag: this flag mo nitors the rtc_1sec interrupt. it is set by hardware and must be cleared by the in terrupt handler bit 7 ( wd_rst ): wd timer reset: the wdt is reset when a 1 is written to this bit. intbits int0int6 0xf8 r interrupt inputs. the m pu may read these bits to see the input to external interrupts int0, int1, up to int6. these bits do not have any memory and are primarily intended for debug use table 12 : special function registers instruction set all instructions of the generic 8051 microcontroller are supported. a complete list of the ins truction set and of the associated op - codes is contained in the 651x software users guide (sug). uart the 71m6511 includes a uart (uart0) that can be programmed to communicate with a variety of amr modules. a second uart (uart1) is connected to the optical port, as described in the optical port description. the uart is a dedicated 2 - wire serial interface, which can communicate with an exter nal host processor at up to 38,400 bits/ s ((with mpu clock = 1.2288mhz). the operation of each pin is as follows: rx : serial input data are applied at this pin. conforming to rs - 232 standard, the bytes are input lsb first. the voltage applied at rx must not exceed 3.6v. tx : this pin is used to o utput the serial data. the bytes are output lsb first. the 71m6511 has , several uart - related registers for the control and buffering of serial data. downloaded from: http:///
71m6511/71m6511h single - phase energy meter ic data sheet november 20 10 page: 22 of 98 ? 2005 C 2010 teridian semiconductor corporation v2.7 a maxim integrated products brand a single sfr register serves as both the transmit buffer and r eceive buffer ( s0buf , sfr 0x99 for uart0 and s1buf , sfr 0x9c for uart1). when written by the mpu, sxbuf acts as the transmit buffer, and when read by the mpu, it acts as the receive buffer. writing data to the transmit buffer starts the transmission b y the associated uart. received data are available by reading from the receive buffer. both uarts can si multaneously transmit and receive data. wdcon[7] selects whether timer 1 or the internal baud rate generator is use d. all uart transfers are programmable for parity enable, parity, 2 stop bits/1 stop bit and xon/xoff options for variable communication baud rates from 300 to 38400 bps. table 13 shows how the baud rates are calculated. tabl e 14 shows the selectable uart operation modes. using timer 1 using internal baud rate generator serial interface 0 2 smod * f ckmpu / (384 * (256 - th1)) 2 smod * f ckmpu /(64 * (2 10 - s0rel)) serial interface 1 n/a f ckmpu /(32 * (2 10 - s1rel)) note: s0rel and s1rel are 10 - bit values derived by combining bits from the respective timer reload registers. smod is the smod bit in the sfr pcon . th1 is the high byte of timer 1. table 13 : baud rate generation uart 0 uart 1 mode 0 n/a start b it, 8 data bits, parity, stop bit, variable baud rate (internal baud rate generator) mode 1 start bit, 8 data bits, stop bit, variable baud rate (internal baud rate generator or timer 1) start bit, 8 data bits, stop bit, variable baud rate (internal baud rate generator) mode 2 start bit, 8 data bits, parity, stop bit, fixed baud rate 1/32 or 1/64 of f ckmpu n/a mode 3 start bit, 8 data bits, parity, stop bit, variable baud rate (internal baud rate generator or timer 1) n/a table 14 : uart modes parity of serial data is available through the p flag of the accumulator. seven - bit serial modes with parity, such as those used by the flag protocol, can be simulated by setting and reading bit 7 of 8 - bit output data. seven - bit serial modes without parity can be simulated by setting bit 7 to a constant 1. 8 - bit serial modes with parity can be simulated by setting and reading th e 9 th bit, using the control bits tb80 (s0con.3) and tb81 (s1con.3) in the s0con and s 1con sfrs for transmit and rb81 (s1con.2) for receive operations. sm20 (s0con.5) and sm21 (s1con.5) can be used as handshake s ignals for inter - pro - cessor communication in multi - processor systems. serial interface 0 control register (s0con). the function of the uart0 depends on the setting of the serial port control register s0con. msb lsb sm0 sm1 sm20 ren0 tb80 rb80 ti0 ri0 table 15 : the s0con register downloaded from: http:///
71m6511/71m6511h single - phase energy meter ic data sheet november 20 10 page: 23 of 98 ? 2005 C 2010 teridian semiconductor corporation v2.7 a maxim integrated products brand serial interface 1 control register (s1con). the function of the serial port depends on the setting of the serial port control register s1con. msb lsb sm - sm21 ren1 tb81 rb81 ti1 ri1 table 16 : the s1con register bit symbol function s0con.7 sm0 these two bits set the uart0 mode: mode description sm0 sm1 0 n/a 0 0 1 8- bit uart 0 1 2 9- bit uart 1 0 3 9- bit uart 1 1 s0con.6 sm1 s0con.5 sm20 enables the inter - processor communication feature. s0con.4 ren0 if set, enables serial reception. cleared by software to disabl e reception. s0con.3 tb80 the 9 th transmitted data bit in modes 2 and 3. set or cleared by the mpu, depending on the function it performs (parity check, multi pro cessor communication etc.) s0con.2 rb80 in modes 2 and 3 it is the 9 th data bit received. in mode 1, if sm20 is 0, rb80 is the stop bit. in mode 0 this bit i s not used. must be cleared by software s0con.1 ti0 transmit interrupt flag, set by hardware after completion of a s erial transfer. must be cleared by software. s0con.0 ri0 receive interrupt flag, set by hardware after completion of a seri al reception. m ust be cleared by software table 17 : the s0con bit functions note: the speed in mode 2 depends on the smod bit in the sfr pcon . see the pcon register description. downloaded from: http:///
71m6511/71m6511h single - phase energy meter ic data sheet november 20 10 page: 24 of 98 ? 2005 C 2010 teridian semiconductor corporation v2.7 a maxim integrated products brand bit symbol function s1con.7 sm sets the baud rate for uart1 sm m ode description baud rate 0 a 9- bit uart variable 1 b 8- bit uart variable s1con.5 sm21 enables the inter - processor communication feature. s1con.4 ren1 if set, enables serial reception. cleared by software to disabl e reception. s1con.3 tb81 the 9 th t ransmitted data bit in mode a. set or cleared by the mpu, depending on the function it performs (parity check, multiprocessor communication etc.) s1con.2 rb81 in modes 2 and 3, it is the 9 th data bit received. in mode b, if sm 21 is 0, rb 81 is the stop bit. must be cleared by software s1con.1 ti1 transmit interrupt flag, set by hardware after completion of a s erial transfer. must be cleared by software. s1con.0 ri1 receive interrupt flag, set by hardware after completion of a seri al reception. must be cleared by software table 18 : the s1con bit functions timers and counters the 80515 has two 16 - bit timer/counter registers: timer 0 and timer 1. these regist ers can be configured for counter or timer operations. in timer mode, the register is incremented every machine cycle meaning that it counts up aft er every 12 periods of the mpu clock signal. in counter mode, the register is incremented when the falling edge is observed at t he corresponding input signal t0 or t1 ( t0 and t1 are the timer gating inputs derived from certain dio pins, see the dio ports chap ter). since it takes 2 machine cycles to recognize a 1 - to - 0 event, the maximum input count rate is 1/2 of the oscillator frequency. there ar e no restrictions on the duty cycle, ho wever to ensure proper recognition of 0 or 1 state, an input should b e stable for at least 1 machine cycle. four operating modes can be selected for timer 0 and timer 1. two special function regis ters ( tmod and tcon ) are used to select the appropriate mode . timer/counter mode control r egister ( tmod ): msb lsb gate c/t m1 m0 gate c/t m1 m0 timer 1 timer 0 table 19 : the tmod register bits tr1 ( tcon.6 ) and tr0 ( tcon .4) in the tcon register (see table 22 and table 23 ) start their associated timers when set. downloaded from: http:///
71m6511/71m6511h single - phase energy meter ic data sheet november 20 10 page: 25 of 98 ? 2005 C 2010 teridian semiconductor corporation v2.7 a maxim integrated products brand bit symbol function tmod.7 tmod.3 gate if set, enables external gate control (pin int0 or int1 for count er 0 or 1, respectively). when int0 or int1 is high, and trx bit is set ( see tcon register), a counter is incremented every falling edge on t0 or t1 input pin tmod.6 tmod.2 c/t selects timer or counter operation. when set to 1, a counter oper ation is performed. when cleared to 0, the corresponding register will funct ion as a t imer. tmod.5 tmod.1 m1 selects the mode for timer/counter 0 or timer/counter 1, as shown in tmod description. tmod.4 tmod.0 m0 selects the mode for timer/counter 0 or timer/counter 1, as shown in tmod description. table 20 : tmo d register bit description m1 m0 mode function 0 0 mode 0 13 - bit counter/timer with 5 lower bits in the tl0 or tl1 register and the remaining 8 bits in the th0 or th1 register (for timer 0 and timer 1, respectively). the 3 high order bits of tl0 and tl1 are held at zero. 0 1 mode 1 16 - bit counter/timer. 1 0 mode2 8- bit auto - reload counter/timer. the reload value is kept in th0 or th1 , while tl0 or tl1 is incremented every machine cycle. when tl (x) overflows, a value from th (x) is copied to tl (x). 1 1 m ode3 if timer 1 m1 and m0 bits are set to '1', timer 1 stops. if timer 0 m1 and m0 bits are set to '1', timer 0 acts as two independent 8 - bit timer/counters. table 21 : timers/counters mode description note: tl0 is affected by tr0 and gate control bits, and sets tf0 flag on overflow. th0 is affected by tr1 bit, and sets tf1 flag on overflow. timer/counter control register ( tcon ) msb lsb tf1 tr1 tf0 tr0 ie1 it1 ie0 it0 table 22 : the tcon register downloaded from: http:///
71m6511/71m6511h single - phase energy meter ic data sheet november 20 10 page: 26 of 98 ? 2005 C 2010 teridian semiconductor corporation v2.7 a maxim integrated products brand bit symb ol function tcon.7 tf1 the timer 1 overflow flag is set by hardware when timer 1 overfl ows. this flag can be cleared by software and is automatically cleared when an int errupt is processed. tcon.6 tr1 timer 1 run control bit. if cleared, timer 1 stops. tcon.5 tf0 timer 0 overflow flag set by hardware when timer 0 overflows . this flag can be cleared by software and is automatically cleared when an interrupt is processed. tcon.4 tr0 timer 0 run control bit. if cleared, timer 0 stops. tcon.3 ie1 interrupt 1 edge flag is set by hardware when the falling edge on external pin int1 is observed. cleared when an interrupt is processed. tcon.2 it1 interrupt 1 type control bit. selects either the falling edge or low level on input pin to cause an interrupt. tcon .1 ie0 interrupt 0 edge flag is set by hardware when the falling edge on ext ernal pin int0 is observed. cleared when an interrupt is processed. tcon.0 it0 interrupt 0 type control bit. selects either the falling edge or low level on input pin to cause int errupt. table 23 : the tcon register bit functions table 24 specifies the combinations of operation modes allowed for timer 0 and timer 1: timer 1 mode 0 mode 1 mode 2 timer 0 - mode 0 yes yes yes time r 0 - mode 1 yes yes yes timer 0 - mode 2 not allowed not allowed yes table 24 : timer modes timer/counter mode control r egister ( pcon ): msb lsb smod table 25 : the pcon register the smod bit in the pcon register doubles the baud rate when set. wd timer (software watchdog timer) the software watchdog timer is a 16 - bit counter that is incremented once every 24 or 384 clock cycles. after a reset, the watchdog timer is disabled and all registers are set to zero. the watchdog consists of a 16 - bit counter (wdt), a reload register ( wdtrel ), prescalers (by 2 and by 16), and control logic. once the watchdog is started, i t cannot be stopped unless the internal reset signal becomes active. note: it is recommended to use the hardware watchdog timer in stead of the software watchdog timer. wd timer start procedure: the wdt is started by setting the swdt flag. when the wdt register enters the state 0x7cff, an asynchronous wdts signal will become active. the signal wd ts sets bit 6 in the ip0 register and requests a reset state. wdts is cleared either by the reset signal or by changing the s tate of the wdt timer. downloaded from: http:///
71m6511/71m6511h single - phase energy meter ic data sheet november 20 10 page: 27 of 98 ? 2005 C 2010 teridian semiconductor corporation v2.7 a maxim integrated products brand refreshing the wd timer: the watchdog timer must be refreshed regularly to prevent the r eset request signal from becoming active. this requirement imposes an obligation on the programmer to issue tw o instructions. the first instruction sets wdt and the second instruction sets swdt . the maximum delay allowed between setting wdt and swdt is 12 clock cycles. if thi s period has expired and swdt has not been set, wdt is automatically reset, otherwise the watchdog timer is reloaded with the content of the wdtrel register and wdt is automatically reset. since the wdt requires exact timing, firmware needs to be designed with special care in order to avoid unwanted wdt resets. teridian strongly discourages the use of the software wdt. special function registers for the wd timer interrupt enable 0 register ( ien0 ): msb lsb eal wdt et2 es0 et1 ex1 et0 ex0 table 26 : the ien0 register (see also table 34) bit symbol function ien0.6 wdt watchdog timer refresh flag. set to initiate a refresh of the watchdog timer. must be set direc tly before swdt is set to prevent an unintentional refresh of the watchdog timer. wdt is reset by hardware 12 clock cycles after it has been set. table 27 : the ien0 bit functions (see also table 34) note: the remaining bits in the ien0 register are not used for watchdog control interrupt enable 1 register ( ien1 ): msb lsb exen2 swdt ex6 ex5 ex4 ex3 ex2 table 28 : the ien1 register (see also tables 35/36) bit symbol function ien1.6 swdt watchdog timer start/refresh flag. set to activate/refresh the watchdog timer. when directly set after setting wdt , a watchdog timer refresh is performed. bit swdt is reset by the hardware 12 clock cycles after it has been set. table 29 : the ien1 bit functions (see also tables 35/36) note: the remaining bits in the ien1 regis ter are not used for watchdog control downloaded from: http:///
71m6511/71m6511h single - phase energy meter ic data sheet november 20 10 page: 28 of 98 ? 2005 C 2010 teridian semiconductor corporation v2.7 a maxim integrated products brand interrupt priority 0 register ( ip0 ): msb lsb -- wdts ip0.5 ip0.4 ip0.3 ip0.2 ip0.1 ip0.0 table 30 : the ip0 register (see also table 46) bit symbol function ip0.6 wdts watchdog timer status f lag. set when the watchdog timer was started. can be read by software. table 31 : the ip0 bit functions (see also table 46) note: the remaining bits in the ip0 register are not used for watchdog control watchdog timer reload registe r ( wdtrel ): msb lsb 7 6 5 4 3 2 1 0 table 32 : the wdtrel register bit symbol function wdtrel.7 7 prescaler select bit. when set, the watchdog is clocked throu gh an additional divide - by - 16 prescaler wdtrel.6 to wdtrel.0 6-0 seve n bit reload value for the high - byte of the watchdog timer. this value is loaded to the wdt when a refresh is triggered by a consecutive sett ing of bits wdt and swdt . table 33 : the wdtrel bit functions the wdtrel register can be lo aded and read at any time. downloaded from: http:///
71m6511/71m6511h single - phase energy meter ic data sheet november 20 10 page: 29 of 98 ? 2005 C 2010 teridian semiconductor corporation v2.7 a maxim integrated products brand interrupts the 80515 provides 11 interrupt sources with four priority levels. each source has its own request flag(s) located in a special function register ( tcon , ircon , and scon ). each interrupt requested by the corresponding flag can be individually e nabled or disabled by the enable bits in sfrs ien0 , ien1 , and ien2 . external interrupts are the interrupts external to the 80515 core , i.e. signals that originate in other parts of the 71m6511/6511h, for example the ce, dio, rtc e eprom interface, comparators. interrupt overview: when an interrupt occurs, the mpu will vector to the predetermine d address as shown in table 51 . once interrupt service has begun, it can be interrupted only by a higher priorit y i nterrupt. the interrupt service is terminated by a return from instruction, "reti". when a reti instruction is perf ormed, the processor will return to the instruction that woul d have been next when the interrupt occurred. when the interrupt condition occurs, the processor will also indicate this by se tting a flag bit. this bit is set regardless of whether the interrupt is enabled or disabled. each interrupt flag is sampled o nce per machine cycle, then samples are polled by the hardware. if the sample indica tes a pending interrupt when the interrupt is enabled, then the inter rupt request flag is set. on the next instruction cycle, the interrupt will be acknowledged by hardware forcing an lca ll to the appropriate vector address, if the following conditions are met: ? no interrupt of equal or higher priority is already in progress. ? an instruction is currently being executed and is not completed. ? the instruction in progress is not reti or any write access to t he registers ien0, ien1, ien2, ip0 or ip1. interrupt res ponse will require a varying amount of time depending on the state of the mpu when the interrupt occurs. if the mpu is performing an interrupt service with equal or greater priority, the new i nterrupt will not be invoked. in other cases, the response time depends on the current instruction. the fastest possible response to an interrupt is 7 machine cycles. this includes one machine cycle for detecting the interrupt and six cycl es to perform the lcall. special function registers for interrupts: interrupt ena ble 0 register ( ie0 ) msb lsb eal wdt es0 et1 ex1 et0 ex0 table 34 : the ien0 register bit symbol function ien0.7 eal eal =0 C disable all interrupts ien0.6 wdt not used for interrupt control es0 =0 C disable serial channel 0 interrupt downloaded from: http:///
71m6511/71m6511h single - phase energy meter ic data sheet november 20 10 page: 30 of 98 ? 2005 C 2010 teridian semiconductor corporation v2.7 a maxim integrated products brand et1 =0 C disable timer 1 overflow interrupt ex1 =0 C disable external interrupt 1 et0 =0 C disable timer 0 overflow interrupt ex0 =0 C disable external interrupt 0 table 35 : the ien0 bit functions downloaded from: http:///
71m6511/71m6511h single - phase energy meter ic data sheet november 20 10 page: 31 of 98 ? 2005 C 2010 teridian semiconductor corporation v2.7 a maxim integrated products brand interrupt enable 1 register ( ien1 ) msb lsb swdt ex6 ex5 ex4 ex3 ex2 table 36 : the ien1 register bit symbol function ien1.7 - ien1.6 swdt not used for interrupt control ien1.5 ex6 ex6 =0 C disable external interrupt 6 ien1.4 ex5 ex5 =0 C disable external interrupt 5 ien1.3 ex4 ex4 =0 C disable external interrupt 4 ien1.2 ex3 ex3 =0 C disable external interrupt 3 ien1.1 ex2 ex2 =0 C disable external interrupt 2 ien1.0 - table 37 : the ien1 bit functions interrupt enable 2 register ( ie2 ) msb lsb - - - - - - - es1 table 38 : the ien2 register bit symbol function ien2.0 es1 es1 =0 C disable serial channel 1 interrupt table 39 : the ien2 bit functions downloaded from: http:///
71m6511/71m6511h single - phase energy meter ic data sheet november 20 10 page: 32 of 98 ? 2005 C 2010 teridian semiconductor corporation v2.7 a maxim integrated products brand timer/counter control r egister ( tcon ) msb lsb tf1 tr1 tf0 tr0 ie1 it1 ie0 it0 table 40 : the tcon register bit symbol function tcon.7 tf1 timer 1 overflow flag tcon.6 tr1 not used for interrupt con trol tcon.5 tf0 timer 0 overflow flag tcon.4 tr0 not used for interrupt control tcon.3 ie1 external interrupt 1 flag tcon.2 it1 external interrupt 1 type control bit tcon.1 ie0 external interrupt 0 flag tcon.0 it0 external interrupt 0 type control bi t table 41 : the tcon bit functions interrupt request register ( ircon ) msb lsb ex6 iex5 iex4 iex3 iex2 table 42 : the ircon register bit symbol function ircon.7 - ircon.6 - ircon.5 iex6 external inter rupt 6 edge flag ircon.4 iex5 external interrupt 5 edge flag ircon.3 iex4 external interrupt 4 edge flag ircon.2 iex3 external interrupt 3 edge flag ircon.1 iex2 external interrupt 2 edge flag ircon.0 - table 43 : the ircon bi t functions note: only tf0 and tf1 (timer 0 and timer 1 overflow flag) will be automatically cleared by hardwar e when the service routine is called (signals t0ack and t1ack C port isr C active high when the service routine is called). external interrupts t he external interrupts are connected as shown in table 44 . the po larity of interrupts 2 and 3 is programmable in the mpu. interrupts 2 and 3 should be programmed for falling sensitivity. the generic 8051 mpu literature states tha t interrupts 4 through 6 are defined as rising edge sensitive. thus, the hardware si gnals attached to interrupts 5 and 6 are inverted to achieve the edge polarity shown in table 44 . sfr (special function register) enable bits must be set to permit any of these interrupts to occur. likewise, each interrupt has its own flag bit that is set by the interrupt hardware and is reset automatically by the mpu interrupt handler (0 through 5). downloaded from: http:///
71m6511/71m6511h single - phase energy meter ic data sheet november 20 10 page: 33 of 98 ? 2005 C 2010 teridian semiconductor corporation v2.7 a maxim integrated products brand xfer_busy and rtc_1sec, which are or - ed together, have their own enable and flag bits in addition to the interrupt 6 enable and flag bits (see table 45 ), and these interrupts must be cleared by the mpu software. external interrupt connection polarity flag reset 0 digital i/o h igh priority see dio_rx automatic 1 digital i/o low priority see dio_rx automatic 2 comparator 2 or 3 falling automatic 3 ce_busy falling automatic 4 comparator 2 or 3 rising automatic 5 eeprom busy falling automatic 6 xfer_busy or rtc_1sec falling m anual table 44 : external mpu interrupts interrupt 6 is edge -sensitive. the rtc_1sec interrupt from the rtc and the xfer_busy interrupt from the ce are com - bined using a logic or function and the result is routed into interrupt 6. therefore, both flags must be cleared at least once during initialization, and both flags must always be cleared before exiting the interrupt service routine (isr) for interrupt 6. note 1: if clearing of both flags is not performed, then no edge can occur to trigger interrupt 6 later resulting in the isr for the xfer_busy ceasing to run. note 2: clearing both flags reliably requires some care. either flag can be set by hardware while interrupt 6 code is running on behalf of the other interrupt. in this situ ation, the unprocessed interrupt can create a lockout condition simi lar to the one in note 1. to prevent this lockout one must always process both interru pt flags in the same service routine. note 3: after a reset from an in - circuit emulator, the ie_xfer f lag may not be cleared because the ce may continue to run. the flags for the rtc_1sec and the xfer_busy interrupts are located in the wdi sfr (address 0xe8). enable bit description flag bit description ex0 enable external interrupt 0 ie0 external inter rupt 0 flag ex1 enable external interrupt 1 ie1 external interrupt 1 flag ex2 enable external interrupt 2 iex2 external interrupt 2 flag ex3 enable external interrupt 3 iex3 external interrupt 3 flag ex4 enable external interrupt 4 iex4 external in terrupt 4 flag ex5 enable external interrupt 5 iex5 external interrupt 5 flag ex6 enable external interrupt 6 iex6 external interrupt 6 flag ex_xfer enable xfer_busy interrupt ie_xfer xfer_busy interrupt flag ex_rtc enable rtc_1sec interrupt ie_rtc rtc_1sec interrupt flag table 45 : control bits for external interrupts downloaded from: http:///
71m6511/71m6511h single - phase energy meter ic data sheet november 20 10 page: 34 of 98 ? 2005 C 2010 teridian semiconductor corporation v2.7 a maxim integrated products brand interrupt priority level structure all interrupt sources are combined in groups, as shown in table 46 : group 0 external interrup t 0 serial channel 1 interrupt 1 timer 0 interrupt - external interrupt 2 2 external interrupt 1 - external interrupt 3 3 timer 1 interrupt - external interrupt 4 4 serial channel 0 interrupt - external interrupt 5 5 - - external interrupt 6 table 46 : priority level groups each group of interrupt sources can be programmed individually to one of four priority lev els by setting or clearing one bit in the special function register ip0 and one in ip1 . if requests of the same priority level are received simultaneously, an inter nal polling sequence as per table 50 determines which request is serviced first. ien enable bits must be set to permit any of these interrupts to occur. likewise, each interrupt has its own flag bit that is set b y the interrupt hardware and is reset automatically by the mpu interrupt handler (0 th rough 5). xfer_busy and rtc_1sec, which are or - ed together, have their own enable and flag bits in addition to the inte rrupt 6 enable and fla g bits (see table 45 ), and these interrupts must be cleared by the mpu software. an overview of the interrupt structure is given in figure 7. interrupt priority 0 register ( ip0 ) msb lsb -- wdts ip0.5 ip0. 4 ip0.3 ip0.2 ip0.1 ip0.0 table 47 : the ip0 register: note: wdts is not used for interrupt controls interrupt priority 1 register ( ip1 ) msb lsb - - ip1.5 ip1.4 ip1.3 ip1.2 ip1.1 ip1.0 table 48 : the ip1 regi ster: ip1.x ip0.x priority level 0 0 level0 (lowest) 0 1 level1 1 0 level2 1 1 level3 (highest) table 49 : priority levels downloaded from: http:///
71m6511/71m6511h single - phase energy meter ic data sheet november 20 10 page: 35 of 98 ? 2005 C 2010 teridian semiconductor corporation v2.7 a maxim integrated products brand external interrupt 0 polling sequence serial channel 1 interrupt timer 0 interrupt external inte rrupt 2 external interrupt 1 external interrupt 3 timer 1 interrupt external interrupt 4 serial channel 0 interrupt external interrupt 5 external interrupt 6 table 50 : interrupt polling sequence interrupt sources and vectors table 51 shows the interrupts with their associated flags and vector addres ses. interrupt request flag description interrupt vector address ie0 external interrupt 0 0x0003 tf0 timer 0 interrupt 0x000b ie1 external inte rrupt 1 0x0013 tf1 timer 1 interrupt 0x001b ri0/ti0 serial channel 0 interrupt 0x0023 ri1/ti1 serial channel 1 interrupt 0x0083 iex2 external interrupt 2 0x004b iex3 external interrupt 3 0x0053 iex4 external interrupt 4 0x005b iex5 external interrup t 5 0x0063 iex6 external interrupt 6 0x006b table 51 : interrupt vectors downloaded from: http:///
71m6511/71m6511h single - phase energy meter ic data sheet november 20 10 page: 36 of 98 ? 2005 C 2010 teridian semiconductor corporation v2.7 a maxim integrated products brand ie0 external interrupt flags ri1 ti1 internal interrupt flags source >=1 tf0 int2 ie1 int3 tf1 int4 ri0 ti0 >=1 int5 int6 >=1 ircon.1 i2fr ircon.2 i3fr ircon.3 ircon.4 ircon.5 ien0.7 ip1.0/ ip0.0 ip1.1/ ip0.1 ip1.2/ ip0.2 ip1.3/ ip0.3 ip1.4/ ip0.4 ip1.5/ ip0.5 interrupt control register priority assignment interrupt vector polling sequence interrupt enable logic and polarity selection dio uart1 (optical) timer 0 com par- ators com par- ators dio timer 1 ce_busy uart0 eeprom/ i2c xfer_busy rtc_1s ien0.0 ien2.0 ien0.1 ien1.1 ien0.2 ien1.2 ien0.3 ien1.3 ien0.4 ien1.4 ien1.5 figure 7 : interrupt structure downloaded from: http:///
71m6511/71m6511h single - phase energy meter ic data sheet november 20 10 page: 37 of 98 ? 2005 C 2010 teridian semiconductor corporation v2.7 a maxim integrated products brand on - chip resources dio ports the 71m6511/6511h includes up to 12 pins of general purpose digital i/o. these pins are dual function and can alt ernatively be used as lcd drivers. figure 8 shows a block diagram of the dio section. on reset or power - up, all dio pins are inputs until they are configured for the desired direction. the pins are configured and con trolled by the dio and dio_dir registers (sfrs) and by the five bits of the i/o register lcd_num (0x2020[4:0]). see the description for lcd_num in the i/o ram section for a table listing the available segment pins versu s dio pins, depending on the selection for lcd_num . generally, increasing the value for lcd_num will configure an increasing number of general purpose pins to be lcd segment pins, starting at the higher pin numbers . com0..3 lcd display driver digital i/o lcd_en lcd_clk lcd_mode dio_gp seg34/dio14 ... seg37/dio17 lcd_num dio_out dio_in lcd_num pulsev/w seg24/dio4 ... seg31/dio11 seg0..seg2 dio_eex seg3/sclk seg4/ssdata seg5/sfr seg6/srdy seg7/ mux_sync seg8..seg19 figure 8 : dio por ts block diagram each pin declared as dio can be configured independently as an input or output with the bits of the dio_dirn registers. table 52 lists the direction registers and configurability associated with e ach group of dio pins. table 53 shows the con figuration for a dio pin through its associated bit in its dio_dir register. dio 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 pin number -- -- -- -- 37 38 39 40 41 42 43 44 -- -- 20 21 data register bit -- -- -- -- 4 5 6 7 0 1 2 3 -- -- 6 7 dio0=p0 (sfr 0x80) dio1=p1 (sfr 0x90) direction re gister bit -- -- -- -- 4 5 6 7 0 1 2 3 -- -- 6 7 dio_dir0 (sfr 0xa2) dio_dir1 (sfr 0x91) internal re sources con figurable -- -- -- -- y y y y y y y y -- -- n n dio 16 17 18 19 20 21 22 23 pin number 22 12 -- -- -- -- -- -- data register bit 0 1 -- -- -- -- -- -- dio2=p2 (sfr 0xa0) direction re gister bit 0 1 -- -- -- -- -- -- dio_dir2 (sfr 0xa1) internal re sources con figurable n n -- -- -- -- -- -- ta ble 52 : data/direction registers and internal resources for dio p in groups downloaded from: http:///
71m6511/71m6511h single - phase energy meter ic data sheet november 20 10 page: 38 of 98 ? 2005 C 2010 teridian semiconductor corporation v2.7 a maxim integrated products brand dio_dir bit 0 1 dio pin function input output table 53 : dio_dir control bit values read from and written into the dio ports use the data registers p0 , p1 and p2 . a 3 - bit configuration word, i/o ram register, dio_rx (0x2009[2:0] through 0x200e[6:4]) can be used for certain pins, when configured as dio, to individually assign an internal resource such as an interrupt or a timer con trol (see table 52 for dio pins available for this option). this way, dio pins can be tracked even if they are configured as outputs. this feature is useful for pulse counting. the control resources selectable for the dio pins a re listed in table 54 . if more than one input is connected to the same resource, the resources are combined using a logical or. dio_r value resource selected for dio pin 0 none 1 reserved 2 t0 (counter0 clock) 3 t1 (counter1 cl ock) 4 high priority i/o interrupt (int0 rising) 5 low priority i/o interrupt (int1 rising) 6 high priority i/o interrupt (int0 falling) 7 low priority i/o interrupt (int1 falling) table 54 : selectable controls using the dio_di r bits additionally, if dio6 and dio7 are declared outputs, they can be configure d as dedicated pulse outputs (wpulse = dio6, varpulse = dio7) using the i/o ram registers dio_pw (0x2008[2]) and dio_pv (0x2008[3]). in this case, dio6 and dio7 are under ce c ontrol. dio4 and dio5 can be configured to implement the eeprom interface by s etting the i/o ram register dio_eex (0x2008[4]). physical memory data bus address space is allocated to on - chip memory as shown in table 55 . address (he x) memory technology memory type typical usage wait states (at 5mhz) memory size (bytes) 0000 - ffff flash memory non - volatile program and non - volatile data 0 64kb 0000 - 07ff static ram battery - buffered mpu data 0 2kb 1000 - 13ff static ram volatile ce dat a 5 1kb 2000 - 20ff static ram volatile configuration ram (i/o ram) 0 256 3000 - 3fff static ram volatile ce program code 5 4kb table 55 : mpu data memory map flash memory: the 71m6511 includes 64kb of on - chip flash memory. the flash memory is intended to primarily contain mpu program code. in a typical application, it also contains images of the ce progra m code, ce co efficients, mpu ram, and i/o ram. on power - up, before enabling the ce, the mpu must copy these images to their respec tive memory locations. downloaded from: http:///
71m6511/71m6511h single - phase energy meter ic data sheet november 20 10 page: 39 of 98 ? 2005 C 2010 teridian semiconductor corporation v2.7 a maxim integrated products brand the i/o ram bit register flash66z defines the pulse width for accessing flash memory. to minimize supply current draw, this bit should be set to 1 . flash erasure is initiated by writing a specific data pattern to specific sfr registers in the proper sequence. these special pattern/sequence requirements prevent inadvertent erasure of the fl ash memory. the mass erase sequence is: 1. write 1 to the flsh_meen bit (sfr address 0xb2[1]. 2. write pattern 0xaa to flsh_erase (sfr address 0x94) note: the mass erase cycle can only be initiated when the ice port is e nabled. the page erase sequence is: 1. write the page address to flsh_pgadr (sfr address 0xb7[7:1] 2. write pattern 0x55 to flsh_erase (sfr address 0x94) writing to flash memory: the mpu may write to the flash memory for non - volatile data storage or when implementing a boot - loader. the i/o ram register flsh_pwe (flash program write enable, sfr b2[0]) differentiates 80515 data store instr uctions (movx@dptr,a) between f lash and xram writes. before s etting flsh_pwe , all interrupts need to be disabled by setting eal =1. after the write operation, flsh_pwe must be cleared. the original state of a flash byte is 0xff (all bits are 1). over writing programmed flash cells with a different value usually re - q uires that the cell is erased first. since cells cannot be erased individually , the page has to be copied to ram, followed by a page erase. after this, the page can be updated in ram and then writte n back to the flash memory. writing to flash locations will affect the corresponding xram cel ls, i.e. 0x2000 to 0x20ff (i/o ram), 0x0000 to 0x07ff (mpu ram), plus ce dram and ce pram. it is critical to maintain the integrity of the cells 0x20000x2007 as a minimum (where important system settings are stored) during the flash - write operation. this can be achieved by excluding the critical addresses from the write operation. mpu ram : the 71m6511 includes 2kb of static ram memory on - chip (xram), which are backed - up by the battery plus 256 - bytes of internal ram in t he mpu core. the 2kb of static ram are used for data storage dur ing normal mpu operations. ce dram: the ce dram is the data memory of the ce. the mpu can read and write the ce dram as the pri mary means of data communication between the two processors. ce pram: the ce pram is the program memory of the ce. the ce pram has to be loaded with ce code bef ore the ce starts operating. ce pram cannot be accessed by the mpu when the c e is running. oscillator the oscillator drives a standard 32.768khz watch crystal ( see figure 9 ). crystals of this type are accurate and do not require a high current oscillator circuit. the oscillator in the teridi an 71m6511 power meter ic has been designed specifically to handle watch crystals and is compatible with their high impedance and limited power handli ng capability. the oscillator power dissipation is very low to maximize the lifetime of any bat tery backup device attached to the vbat pin. downloaded from: http:///
71m6511/71m6511h single - phase energy meter ic data sheet november 20 10 page: 40 of 98 ? 2005 C 2010 teridian semiconductor corporation v2.7 a maxim integrated products brand crystal xout xin 71m651x figure 9 : oscillator circuit the osci llator should be placed as close as possible to the ic, and vias sho uld be avoided. an external resistor across the crystal must not be added. real - time clock (rtc) the rtc is driven directly by the crystal oscillator. in the absence of th e 3.3v supply, th e rtc is powered by the external battery (vbat pin). the rtc consists of a counter chain and output registers. the counter chain consists of seconds, minutes, hours, day of week, day of month, month, and year. the rtc is capable of processi ng leap years. each counter has its own output register. whenever the mpu reads the seconds register, all other output regi sters are automatically updated. since the rtc clock is not coherent to the mpu clock, the mpu must read the seconds regist er until two consecutive reads are the same (requires either 2 or 3 reads). at this point, all rtc output registers wi ll have the correct time. regardless of the mp u clock speed, rtc reads require one wait state. the rtc interrupt must be enabled using the i/o ram register ex_rtc (address 0x2002[1]). rtc time is set by writing to the i/o ram registers rtc_sec , rtc_min, through rtc_yr . each byte written to rtc must be delayed at least 3 ck32 cycles from any previous byte written to rtc. two time correction bits, the i/o ram register s rtc_dec_sec (0x201c[1]) and rtc_inc_sec (0x201c[0]) are provided to adjust the rtc time. a pulse on one of these bits causes the time to be decremented or incremented by an additional second at the next update of the rtc_sec register. thus, if the crysta l temperature coefficient is known, the mpu firmware can integrate temperature and correct the rtc time as necessary as discussed in temperature compensation. lcd drivers the 71m6511 contains 15 dedicated lcd segment pins, 5 lcd segment pins that rare shared with the ssi port and/or other functions, and an additional 12 multi - purpose pins (lcd/dio) that may be configured as lcd segment drivers (see i/ o ram register lcd_num ). thus, the 71m6511/6511h is capable of driving between 80 to 128 pixels of lcd display with 25% dut y cycle. at seven segments per digit, the lcd can be designed for 11 to 18 digits for display. since each pixel is addressed individually, the lcd display can be a combination of alphanumeric dig its and enunciator symbols. the information to be displayed is written into the lower four bits of i/o ram registers lcd_seg0 through lcd_seg37 . bit 0 corresponds to the segment selected when com0 pin is active while bit 1 is allocat ed to com1. the lcd driver circuitry is grouped into four common outp uts (com0 to com3) and up to 32 segment outputs (see table 56 ). downloaded from: http:///
71m6511/71m6511h single - phase energy meter ic data sheet november 20 10 page: 41 of 98 ? 2005 C 2010 teridian semiconductor corporation v2.7 a maxim integrated products brand dedicated segment pins shared w/ dio4 - dio11 shared w/ dio14 - dio17 seg0 seg1 seg19 seg24 seg31 seg34 seg37 com0 p0 p4 p76 p80 p108 p112 p124 com1 p1 p5 p77 p81 p109 p113 ... p125 com2 p2 p6 p78 p82 p110 p114 p126 com3 p3 p7 p79 p83 p111 p115 p127 table 56 : liquid crystal display segment table (typical) note: p0, p1, represent the pixel/segment numbers on th e lcd. a charge pump suitable for driving vlcd is included on - chip. this circuit creates 5v from the 3.3v supply. a contrast dac is provided that permits the lcd full - scale voltage to be adjusted between vlcd and 70% of vlcd. the lcd_num register defines t he number of dual purpose pins used for lcd segment interface. lcd voltage boost circuitry a voltage boost circuit may be used to generate 5v from the 3.3v s upply to support low - power 5v devices, such as lcds. figure 10 shows a bl ock diagram of the voltage boost circuitry including the voltage regulators fo r v2p5 and v2p5nv. when activated using the i/o ram register lcd_bsten (0x2020[7]), the boost circuitry provides an ac voltage at the vdrv output pin (see the applications sectio n for details). gndd v3p3d vbat volt reg 0.1v v2p5 vlcd vdrv voltage boost lcd_bsten lcd_ibst gndd gndd gndd v2p5 v3p3d v2p5nv figure 10 : lcd voltage boost circuitry uart (uart0) and optical port (uart1) the 71m6511/6511h includes an interface to implement an ir or optical port. the pin opt_tx is designed to directly drive an external led for transmitting data on an optical link (low - active). the pin opt_rx, also low -active, is designed to sense the input from an external photo detector used as the receiver for the optical link. these two pins are connected to a dedicated uart port. opt_tx can be tristated if it is desired to multiplex another i/o pin to the opt_t x output. the control bit for the opt_tx output is the i/o ram register opt_txdis (0x2008[5]). downloaded from: http:///
71m6511/71m6511h single - phase energy meter ic data sheet november 20 10 page: 42 of 98 ? 2005 C 2010 teridian semiconductor corporation v2.7 a maxim integrated products brand hardware reset mechanisms several conditions will cause a hardware reset of the 71m6 511/6511h: ? voltage at the resetz pin low ? voltage at the e_rst pin low ? voltage at the v1 pin below reset threshold (vbias) ? the crystal frequency monitor detected a crystal malfunction ? hardware watchdog timer reset pin (resetz) when the resetz pin is pulled low (or when v1 < vbias), all di gital activity in the chip stops while analog circuits are sti ll active. the oscillator and rtc module continue to run. additionally , all i/o ram bits are cleared. hardware watchdog timer in addition to the basic software watchdog timer included in the 80515 mpu, an i n de pendent, robust, fixed - duration, hardware watchdog timer (wdt) is included in the 71m6511/6511h. this timer will reset the mpu i f it is not refreshed periodically, and can be used to recover the mpu in situa tions where program control is lost. the watchdog timer uses the rtc crystal oscillator as its time base and require s a reset under mpu program control at least every 1.5 seconds. when the wdt overflow occurs, the mpu is momentar ily reset as if resetz wer e pulled low for half of a crystal oscillator cycle. thus, after 4100 cycles of the ck32 ( 32768hz clock), the mpu program will be launched from address 00. an i/o ram register status bit, wd_ovf (0x2002[2]), is set when wdt overflow occurs . this bit is powered by the vbat pin and can be read by the mpu to determine if the part is initializing after a wdt overflow ev ent or after a power up. after reading this bit, mpu firmware must clear wd_ovf . the wd_ovf bit is also cleared by the resetz pin. the watchdog timer also includes an oscillator check. if the crystal oscil lator stops or slows down, wd_ovf is set and a system reset will be performed when the crystal oscillator r esumes. there is no internal digital state that deactivates the wdt. for debug purposes, however, the wdt can be disabled by tying the v1 pin to v3p3 (see figure 11 and wd disable threshold [v1 - v3p3a] in the comparator section of the electrical specifications). of course, this also deactivates the power fault detect ion implemented with v1. since there is no way in firm - ware to disable the crystal oscillator or the wdt, it is guara nteed that whatever state the mpu might find itself in, it wil l be reset to a known state upon watchdog timer overflow. in normal operation, the wdt is reset by periodically writing a one to the wdt_rst bit. the watchdog timer is also reset when wake=0 and, during development, when a 0x14 command is received from the ice port. crystal frequency monitor the hardware watchdog timer also includes an oscillator check. if the crystal os cillator stops or slows down, the i/o ram register wd_ovf is set and a system reset will be performed when the crystal oscillator resumes. v1 pin the comparator at the v1 pin controls the state of the digital circuitry o n the chip. when v1 < vbias (or when the restz pin is pulled low), all digital activity in the chip stops while analog circuits inclu ding the oscillator and rtc module are stil l active. additionally, when v1 < vbias, all i/o ram bits are cleared. as long as v1 is g reater than vbias, the internal 2.5v regulator will continue to provide power to the digital section. downloaded from: http:///
71m6511/71m6511h single - phase energy meter ic data sheet november 20 10 page: 43 of 98 ? 2005 C 2010 teridian semiconductor corporation v2.7 a maxim integrated products brand v3p3 v3p3 - 400mv v3p3-10mv vbias 0v battery or reset mode normal operation, wdt enabled wdt dis- abled v1 when (v1 < vbias) the battery is enabled figure 11 : voltage range for v1 i2c interface (eeprom) a dedicated 2 - pin serial interface implements an i2c driver that can be used to communicate with external eeprom devices. the interface can be multiplexed onto the dio pins dio4 (sck) and di o5 (sda) by setting the i/o ram register dio_eex (0x2008[4]). the mpu communicates with the interface through two sfr registe rs: eedata (0x9e) and eectrl (0x9f). if the mpu wishes to write a byte of data to eeprom, it places the data i n eedata and then writes the transmit code to eectrl . the write to eectrl initiates the transmit sequence. by observing the busy bit in eectrl t he mpu can determine when the transmit operation is finished (i.e. when the busy bit transitions from 1 to 0). int5 is also asserted when busy falls. the mpu can then check the rx_ack bit to see if the eeprom acknowledged the transmission. a byte is read by writing the receive command to eectrl and waiting for busy to fall. upon completion, the received data will appear in eedata . the serial transmit and receive clock is 78khz during each transmission, and sc l is held in a high state until the next trans mission. the bits in eectrl are shown in table 57 . the eeprom interface can also be operated by controlling the dio4 and di o5 pins directly. however, controlling dio4 and dio5 directly is discouraged, because it may tie up the mpu to the point where it may become too busy to process interrupts . note: clock stretching and multi - master operation is not supported for the i 2 c interface. downloaded from: http:///
71m6511/71m6511h single - phase energy meter ic data sheet november 20 10 page: 44 of 98 ? 2005 C 2010 teridian semiconductor corporation v2.7 a maxim integrated products brand status bit name read/ write reset state polarity description 7 error r 0 positive 1 when an il legal command is received. 6 busy r 0 positive 1 when serial data bus is busy. 5 rx_ack r 1 negative 0 indicates that the eeprom sent an ack bit. 4 tx_ack r 1 negative 0 indicates when an ack bit has been sent to the eeprom 3-0 cmd[3:0 ] w 0 positive , see cmd table cmd operation 0 no - op. applying the no - op command will stop t he i2c clock (sck, dio4). failure to issue the no - op command will keep the sck signal toggling. 2 receive a byte from eeprom and send ack. 3 transmit a byte to eeprom. 5 issue a stop sequence. 6 receive the last byte from eeprom and do not send ack. 9 issue a start sequence. others no operation, set the error bit. table 57 : eectrl status bits internal clocks and clock dividers all internal clo cks are based on the watch crystal frequency ( ck32 = 32,768hz) applied to the xin and xout pins. the pll multiplies this frequency by 150 to 4.9152mhz. this frequency is supplied to the adc, the fir filter (ckfir), the clock test output pin (cktest), the ce dram and the clock generator. the clock generator provide s two clocks, one for the mpu (ckmpu) and one for the ce (ckce). the mpu clock frequency is determined by the i/o ram register mpu_div (0x2004[2:0]) and can be ce*2 - mpu_div hz where mpu_div varies from 0 to 7 ( mpu_div is 0 on power - up). this makes the mpu clock scalable from 4.9152mhz down to 38.4khz. the circuit also ge nerates a 2x mpu clock for use by the emulator. this clock is not generated when the i/o ram register eck_dis (0x2005[5]) is asserted by the mpu. battery the vbat pin provides an input for an external battery that can be used to support the crystal oscillator, rtc, the wd_ovf bit and xram in the absence of the main power supply. if the battery i s not used, the vbat pin should be con nected to v3p3. internal voltages (vbias, vbat, v2p5) the 71m6511 requires two supply voltages, v3p3a, for the analog section, and v3p3d, for the dig ital section. both voltages can be tied together outside the chip. the internal supply voltage v 2p5 is generated by a regulator from the 3.3v supplies. the battery voltage, vbat, is required when crystal oscillator, rtc and xra m are required to keep operating while v3p3d is removed (battery mode). vbat, usually supplied by an external battery , powers crystal oscillator, rtc and xram (and the wd_ovf bit). vbias (1.5v) is generated internally and used for the v1 comparator and for the reference of the temperature sensor. test ports downloaded from: http:///
71m6511/71m6511h single - phase energy meter ic data sheet november 20 10 page: 45 of 98 ? 2005 C 2010 teridian semiconductor corporation v2.7 a maxim integrated products brand tmuxout pin: one out of 16 digital or 4 analog signals can be selected to be output on the tmuxout pin. the function of the multiplexer is controlled with the i/o ram register tmux (0x2000[3:0]), as shown in table 58 . tmux[3:0] mode function 0 analog dgnd 1 analog ibias 2 analog pll_2.5v 3 analog vbias 4 digital rtm (real time output from ce) 5 digital wdtr_en (comparator 1 output and v1lt3) 6 digital reserved 7 digital reserved 8 digital rxd (from optical interface) 9 digital mux_sync a digital ck_10m b digital ck_mpu c -- reserved for produ ction test d digital rtclk e digital ce_busy f digital xfer_busy table 58 : tmux[3:0] selections emulator port: the emulator port, consisting of the pins e_rst, e_tclk and e_rxtx provides control of the mpu through an external in - circuit emulator. the emulator port is compatible with the adm51 e mulators manufactured by signum systems. the signals of the emulator port have weak pull - ups. adding 1k ? pull - up resistors on the pcb is recommended. real - time monitor: the rtm output of the ce is available as one of the digital multiplexer options. rtm data is read from the ce dram locations specified by i/o ram registers rtm0 , rtm1 , rtm2 , and rtm3 after the rise of mux_sync. the rtm can be enabled and disabled with i/o ram register rtm_en . the rtm output is clocked by cktest. each rtm word is clocked out in 35 cycles and contains a leading flag bit. figure 13 in the system timing section illustrates the rtm output form at. rtm is low when not in use. ssi interfa ce: a high - speed serial interface with handshake capability is available to s end a contiguous block of ce data to an external data logger or dsp. the block of data, configurable as to location and size, is sent starting 1 cycle of 32khz befor e each ce code pass begins. if the block of data is big enough that transmission has not completed when the code pass begins, it will complete during the ce code pass with no timing impact to the ce or the seri al data. in this case, care must be taken that the transmitt ed data is not modified unexpectedly by the ce. the ssi interface is enabled by the ssi_en bit and consists of sclk, ssdata, and sfr as outputs and, optionally, srdy as input. the interface is compatible with 16bit and 32bit processors. the operation of each pin is as follows: sclk is the serial clock. the clock can be 5mhz or 10mhz, as specified by the ssi_10m bit. the ssi_ckgate bit controls whether sclk runs continuously or is gated off when no ssi activity i s occurring. if sclk is gated, it will begin 3 cycles before sfr rises and will persist 3 cycles after the last data bit i s output. the pins used for the ssi are multiplexed with the lcd segment outputs, as shown in table 59 . thus, the lcd should be disabled when the ssi is i n use. downloaded from: http:///
71m6511/71m6511h single - phase energy meter ic data sheet november 20 10 page: 46 of 98 ? 2005 C 2010 teridian semiconductor corporation v2.7 a maxim integrated products brand ssi signal lcd segment output pin sclk seg3 ssdata seg4 sfr seg5 srdy seg6 table 59 : ssi pin assignment srdy is an optional handshake input that indicates that the dsp or data - logging device is ready to receive data. sr dy must be high to enable sfr to rise and initiate the transfer of the next field. it is expected t hat srdy changes state on the risi ng edges of sclk. if srdy is not high when the ssi port is ready to transmit the next field, transmission will be delayed u ntil it is. srdy is ignored except at the beginning of a field transmission. if srdy is no t enabled (by ssi_rdyen ), the ssi port will behave as if srdy is always one. ssdata is the serial output data. ssdata changes on the rising edge of sclk and outputs t he contents of a block of ce ram words starting with address ssi_strt and ending with ssi_end . the words are output msb first. the field size is set with the ssi_fsize register: 0 entire data block, 1 - 8 bit fields, 2 - 16 bit fields, 3 - 32 bit fields. the pol arity of the sfr pulse can be inverted with ssi_fpol . if srdy does not delay it, the first sfr pulse in a frame will rise on the third sclk after mux_sync (fourth sclk if 10mhz). mux_sync can be used t o synchronize the fields arriving at the data logger or dsp. downloaded from: http:///
71m6511/71m6511h single - phase energy meter ic data sheet november 20 10 page: 47 of 98 ? 2005 C 2010 teridian semiconductor corporation v2.7 a maxim integrated products brand functional descripti on theory of operation the energy delivered by a power source into a load can be expressed as: = t dt t i t v e 0 ) ( ) ( assuming phase angles are constant, the following formulae apply: ? p = real energy [wh] = v * a * cos * t ? q = reactive energy [varh] = v * a * sin * t ? s = apparent energy [vah] = 2 2 q p + for a practical meter, not only voltage and current amplitudes, but also phase angles and harmonic con tent may change constantly. thus, simple rms measuremen ts are inherently inaccurate. a modern solid - state electricity meter ic such as the 71m6511/6511h functions by emulating the integral operation above, i.e. it pr ocesses current and voltage samples through an adc at a constant frequency. as long as the adc resolution is hi gh enough and the sample frequency is beyond the harmonic range of interest, the current and voltage samples, multiplied wi th the time period of sampling will yield an accurate quanti ty for the momentary energy. summing up the momentary energy quantities over time will result in accumulated energy. -500 -400 -300 -200 -100 0 100 200 300 400 500 0 5 10 15 20 time [ms] v [v], i [a], p [ws] current [a] voltage [v] energy per interval [ws] accumulated energy [ws] figure 12 : voltage. current, momentary and accumulated energy figure 12 shows the shapes of v(t), i(t), the momentary and the accumulated energy, resulting from 50 samples of the voltage and current signals over a period of 20ms. the application of 240vac and 100a re sults in an accumulation of 480ws over the 20ms period, as indicated by the accumulated power curve. the described sampling method works reliably, even in the presence of dynamic phase shift and harmonic distortion. system timing summary downloaded from: http:///
71m6511/71m6511h single - phase energy meter ic data sheet november 20 10 page: 48 of 98 ? 2005 C 2010 teridian semiconductor corporation v2.7 a maxim integrated products brand figure 13 summarizes the timing relationships between the input mux states, the ce_b usy signal, and the two serial output st reams. in this example, mux_div = 1 (four mux states) and fir_len = 1 (3 ck32 cycles). since fir filter conversions require two or three ck32 cycles, the duration of each mux cycle is 1 + 2 * states defined by mux_div if fir_len = 0, and 1 + 3 * states def ined by mux_div if fir_len = 1. followed by the conversions is a single ck32 cycle. each ce program pass begins when mux_sync falls. depending on the length of the ce program, it may continue running until the end of the adc5 conversion. ce opcodes are co nstructed to ensure that all ce code passes consume exactly the same number of cycles. the result of each adc conversion is inserted into t he ce dram when the conversion is complete. the ce code is designed to tolerate sudden changes in adc data. the exact ck count when each adc value is loaded into dram is shown in figure 13 . figure 13 also shows that the two serial data streams, rtm and ssi, begin transmitting at the beginning of mux_sync. rtm, consistin g of 140 ck cycles, will always finish before the next code pass starts. the ssi port be gins transmitting at the same time as rtm, but may significantly overrun the next code pass if a large block of dat a is required. neither the ce nor the ss i port will b e affected by this overlap. ck32 mux state 0 mux_div conversions ( mux_div =4 is shown) settle adc mux frame adc execution s mux_sync s ce_execution rtm 140 max ck count 0 450 150 900 1350 1800 adc0 adc1 adc2 adc3 ck count = ce_cycles + floor((ce_cycles + 2) / 5) adc, ce and serial timing notes: 1. all dimensions are 5mhz ck counts. 2. the precise frequency of ck is 150*crystal frequency = 4.9152mhz. 3. xfer_busy occurs once every (presamps * sum_cycles) code passes. ce_busy xfer_busy initiated by a ce opcode at end of sum interval adc timing ce timing rtm and ssi timing 1 2 3 begin ssi transfer last ssi transfer ssi figure 13 : timing relationship between adc mux, ce, and serial transf ers figure 14 , figure 15 , and figure 16 show the rtm a nd ssi timing, respectively. downloaded from: http:///
71m6511/71m6511h single - phase energy meter ic data sheet november 20 10 page: 49 of 98 ? 2005 C 2010 teridian semiconductor corporation v2.7 a maxim integrated products brand cktest tmuxout/rtm flag rtm data0 (32 bits) lsb sign lsb sign rtm data1 (32 bits) lsb lsb sign sign rtm data2 (32 bits) rtm data3 (32 bits) 0 1 30 31 0 1 30 31 0 1 30 31 0 1 30 31 flag flag flag mux_sync ck32 figure 14 : rtm output format sclk (output) ssdata (output) sfr (output) srdy (input) 31 30 16 15 1 0 31 ssi_beg 30 16 15 1 0 31 ssi_beg +1 1 0 ssi_end if 16bit fields if 32bit fields if ssi_ckgate =1 if ssi_ckgate =1 mux_sync figure 15 : ssi timing, ( ssi_fpol = ssi_rdypol = 0) sclk (output) ssdata (output) sfr (output) srdy (input) 31 30 16 15 14 13 16 16 16 12 29 18 17 next field is delayed while srdy is low figure 16 : ssi timing, 16 - bit field example (external device delays srdy) sfr is the framing pulse. although ce words are always 32 bits, the ssi inter face will frame the entire data block as a singl e field, as multiple 16 - bit fields, o r as multiple 32 - bit fields. the sfr pulse is one sclk clock cycle wide, changes state on the rising edge of sclk and precedes the first bit of each field. downloaded from: http:///
71m6511/71m6511h single - phase energy meter ic data sheet november 20 10 page: 50 of 98 ? 2005 C 2010 teridian semiconductor corporation v2.7 a maxim integrated products brand data flow the data flow between ce and mpu is shown in figure 17 . in a typical application, the 32 - bit compute engine (ce) sequentially processes the samples from the voltage inputs on pins ia, va, a nd ib, performing calculations to measure active power (wh), reactive power (varh), a 2 h, and v 2 h for four - quadrant metering. thes e measurements are then accessed by the mpu, processed further and output using the peripheral devices avail able to the mpu. ce mpu pre - processor post- processor irq processed metering data pulses i/o ram (configuration ram) samples data figure 17 : mpu/ce data flow ce/mpu communication figure 18 shows the functiona l relationship between ce and mpu. the ce is controlled by the mpu via shared registers in the i/o ram and by registers in the ce dram. the ce outputs two interrupt signals to the m pu: ce_busy and xfer_busy, which are connected to the mpu interrupt service inputs as external interrupts. ce_busy indicates that the ce is actively processing data. this signal will occur once every multiplexer cycle. xfer_busy indicates that the ce is updating data to the output region of the ce ram. this will occur whenever the ce has finished generating a sum by completing an accumulation interval determined by sum_cycles * pre_samps samples. interrupts to the mpu occur on the falling edges of the xfer_busy and ce_busy signals. figure 19 shows the sequence of events between ce and mpu upon reset or power - up. in a typical application, the sequence of events is as follows: 1) upon power - up, the mpu initializes the hardware, including disabling the ce 2) the mpu loads the code for the ce into the ce pram 3) the mp u loads ce data into the ce dram. 4) the mpu starts the ce by setting the ce_en bit in the i/o ram. 5) the ce then repetitively executes its code, generating results and storing them in the ce dram it is important to note that the length of the accu mulation inte rval, as determined by n acc , the product of sum_cycles and pre_samps is not an exact multiple of 1000ms. for example, if sum_cycles = 60, and pre_samps = 00 (42), the resulting accumulation interval is: ms hz hz f n s acc 75. 999 62. 2520 2520 13 32768 42 60 = = ? = = this means that accurate time measurements should be based on the rtc , not the accumulation interval. downloaded from: http:///
71m6511/71m6511h single - phase energy meter ic data sheet november 20 10 page: 51 of 98 ? 2005 C 2010 teridian semiconductor corporation v2.7 a maxim integrated products brand i/o ram (configuration ram) mpu ce pulses data interrupts display (me- mory-mapped lcd segments) dio eeprom (i2c) serial (uart0/1) samples apulsew apulser var (dio7) w (dio6) varsum wsum adc ext_pulse ce_busy xfer_busy mux ctrl. figure 18 : mpu/ce communication (functional) the mpu will wait for the ce to signal that fresh data is ready (the xfer interrupt). it will read the data and perform additional processing such as energy accumulation. ce_en ce pram computation engine ce dram flash mpu xfer interrupt figure 19 : mpu/ce communication (processing sequence) fault, reset, power - up reset mode: when the resetz pin is pulled low or when v1 < vbias, all digital activity in the chip sto ps while analog circuits are still active. the oscillator and rtc module continue to run. additionally, all i/o ram bits are cleared. as long as v1, t he input voltage at the power fault block, is greater than vbias, the internal 2.5v regulator will continue to provide power to the digital section. once initiated, the reset mode will persist until the reset timer times out, s ignified by wake rising. this will occur in 410 0 cycles of the real time clock after resetz goes high, at which time the mpu will begin executing its pre boot and boot sequences from address 00. see the security section for more descr iption of preboot and boot. downloaded from: http:///
71m6511/71m6511h single - phase energy meter ic data sheet november 20 10 page: 52 of 98 ? 2005 C 2010 teridian semiconductor corporation v2.7 a maxim integrated products brand power - up: after power - up, the 71m6511/6511h is in reset as long as v1 < vbias. as soon as v1 exceeds vbias, the reset timer is started which takes the mpu out of reset after 4100 oscillator cy cles (see figure 20 ). the mpu then initiates its pre - boot phase lasting 32 cycles. the supply current will be low but not zero during power - up. it will incr ease, once v1 exceeds vbias and will increase to the nominal value once the preboot phase starts. the supply current may then be reduced under firmware control, following the steps specified in battery ope ration and power save modes. v3p3 v1 supply current 3.3v 1.5v pre- boot reset timer firmware has control over chip... 1ms 0v v2p5 power down v1 > vbias pwr up 0ma nominal 125ms figure 20 : timing diagram for voltages, current and operation modes af ter power - up battery operation when v1 is lower than vbias, the external battery will power t he following parts of the 71m6511/6511h: ? rtc ? crystal oscillator circuitry ? mpu xram ? wd_o vf bit power save modes in normal mode of operation, running on 3.3v supply, various resources of the 71m6511/6511h may be shut down by the mpu firmware in order to reduce power consumption while other essential resources such as uarts may remain active . table 60 outlines these resources and their typical current consumption (bas ed on initial condition mpu_div = 0). power saving measure software control typical savings disable the ce ce_en = 0 0.16ma disable the adc adc_dis = 1 1.8ma disable clock test output cktest ckoutdis = 1 0.6ma disable emulator clock eck_dis = 1 *) 0.1ma set flash read pulse timing to 33 ns flash66z =1 0.04ma disable the lcd voltage boost circuitry lcd_bsten = 0 0.9ma disable rtm outputs rtm_en = 0 0.01ma increase the clock divider for the mpu mpu_div = x 0.4ma/mhz *) this bit is to be used with caution! inadvertently setting this bit will inhibit access to the part with the ice interface and thus preclude flash erase and pro gramming o perations. table 60 : power saving measures downloaded from: http:///
71m6511/71m6511h single - phase energy meter ic data sheet november 20 10 page: 53 of 98 ? 2005 C 2010 teridian semiconductor corporation v2.7 a maxim integrated products brand temperature compensation internal compensation: the internal voltage reference is calibrated during device manufact ure. trim data is stored in on - chip fuses. for the 71m6511, the temperature coefficients tc1 and tc2 are given as c onstants that represent typical com ponent behavior. for the 71m6511h, the temperature characteristics of the chip are measur ed during production and then stored in the fuse registers trimbga, trimbgb and trimm[2:0 ]. tc1 and tc2 can be derived from the fuses by using the relations gi ven in the electrical specifications section. tc1 and tc2 can be further pr ocessed to generate the coefficients ppmc and ppmc2 . trimm[2:0], trimbga and trimbgb are read by first writing either 4, 5 or 6 to trimsel (0x20fd) and then reading the value of trim (0x20ff). when the ext_temp register in ce dram (address 0x38) is set to 0, the ce automatically compensates f or temperature errors by controlling the gain_adj register (address 0x2e) based on the ppmc , ppmc2 , and temp_x register values. in the case of internal compensation, gain_adj is an output of the ce. external compensation : rather than internally compensating for the temperature variation, the bandgap t emperature is provided to the embedded mpu, which then may digitally compensate the power outputs. this permits a system - wide temperature correction over the entire system rather than local to the chip. the i ncorporated thermal coefficients may includ e the current sensors, the voltage sensors, and other influences. since the band gap is chopper stab ilized via the chop_en bits, the most significant long - term drift mechanism in the voltage reference is removed. when the ext_temp register in ce dram is set to 15, the ce ignores the ppmc , ppmc2 , and temp_x register values and applies the gain supplied by the mpu in gain_adj . external compensation enables the mpu to control the ce gain based on any variable, and when ext_temp = 15, gain_adj is an input to the ce. chopping circuitry as expl ained in the hardware section, the bits of the i/o ram register chop_ena[1:0] have to be toggled in between multiplexer cycles to achieve the desired elimination of dc offset . the amplifier within the reference is auto - zeroed by means of an internal signal that is controlled by the chop_en bits. when this signal is high, the connection of the amplifier inputs is reversed. this preserves the overall polarity of the amplifier gain but inverts the input offset. by alternately reversing the conne ction, the offset of the amplifier is averaged to zero. the two bit s of the chop_en register have the function specified in table 61 . chop_en[1] chop_en[0] function 0 0 toggle chop signal 0 1 reference connection positive 1 0 reference connection reversed 1 1 toggle chop signal table 61 : chop_en bits for automatic chopping, the chop_en bits are set to either 00 or 11. in this mode, the polarity of the signals feeding the reference amplifier will be automatically toggled for each multiplexer cyc le as shown in figure 21 . with an even number of multiplexer cycles in each accumulation interval, the number of cy cles with positive reference connection will equal the numb er of cycles with reversed c onnection, and the offset for each sampled signal will be averaged to zero. this sequence is acceptable when only the primary signals (meter voltage, meter curr ent) are of interest. downloaded from: http:///
71m6511/71m6511h single - phase energy meter ic data sheet november 20 10 page: 54 of 98 ? 2005 C 2010 teridian semiconductor corporation v2.7 a maxim integrated products brand accumulation interval m mux cycle n mux cycle 2 mux cycle 3 chop polarity positive positive positive positive re- versed re- versed re- versed re- versed mux cycle n mux cycle 1 mux cycle 1 mux cycle 1 accumulation interval m+1 ce_busy interrupt (falling edge) xfer_busy interrupt (falling edge) accumulation interval m+2 positive positive re- versed figure 21 : chop polarity w/ automatic chopping if temperature compensation or accurate reading of the die temperatur e is required, alternate multiplexer cycles have to be inserted in between the regular cycles. this is done under mpu firmware control by asserting the mux_alt bit whenever necessary. sin ce die temperature usually changes very slowly, alternate multiplexer cyc les have to be inserted very infrequently. usually, an alternate multiplexer cycle is inserted once for every accumulation period, i.e. after each xfer_busy interrupt. this sequence i s shown in figure 22 . accumulation interval m mux cycle n mux cycle 2 mux cycle 3 chop polarity positive positive positive positive re- versed re- versed re- versed re- versed mux cycle n accumulation interval m+1 alt. mux cycle alt. mux cycle alt. mux cycle ce_busy interrupt xfer_busy interrupt accumulation interval m+2 positive positive re- versed mux_alt figure 22 : sequence with alternate multiplexer cycles this sequence has the disadvantage that the alternate multiplexer cycle is alwa ys operated with positive connection. conseque ntly, dc offset will appear on the temperature measurement, which will dec rease the accuracy of this measurement and thus cause temperature reading and compensation to be less accurate. the sequence shown in figure 23 uses the cho p_en bits to control the chopper polarity after each xfer_busy interrupt . chop_en is controlled to alternate between 10 (positive) and 01 (reversed) for the firs t multiplexer cycle following each downloaded from: http:///
71m6511/71m6511h single - phase energy meter ic data sheet november 20 10 page: 55 of 98 ? 2005 C 2010 teridian semiconductor corporation v2.7 a maxim integrated products brand xfer_busy interrupt. after these first two cycles, chop_en r eturns to 11 (automatic toggle). the value of chop_en , when set after the xfer_busy interrupt, is in force for the entire followin g multiplexer cycle. when using this sequence, the alternate multiplexer cycle is toggled betwee n positive and reversed connec tion resulting in accurate temperature measurement. an example for proper application of the chop_en bits can be found in the demo code shipped with the 6511 and 6511 demo kits. firmware implementations should closely follow this example. alt. mux cycle alt. mux cycle alt. mux cycle accumulation interval m accumulation interval m+1 positive positive positive positive positive accumulation interval m+2 positive positive re- versed re- versed re- versed re- versed re- versed mux cycle 2 mux cycle 2 mux cycle 2 mux cycle 3 mux cycle 3 mux cycle 3 mux cycle n mux cycle n mux cycle n chop polarity 01 11 01 11 (11) (11) (11) (11) (11) (11) (11) 10 11 (11) chop_en (11) ce_busy interrupt xfer_busy interrupt mux_alt figure 23 : sequence with alternate multiplexer cycles and controlled chopping internal/external pulse generation and pulse counting the ce is the source for pulses. it can generate pulses directl y based on the voltage and current inputs and the c onfigured pulse generation parameters. this is called internal pulse generati on, and applies when the ce ram register ext_pulse (address 0x37) equals 0. alternatively, the ce can be configured to generate pulses based on r egisters that are controlled by the mpu (external pulse generation), i.e. when the register ext_pulse equals 15. in the case of external pulse generation, the mpu writes values to the ce registers apulsew (0x26) and apulser (0x27). the pulse rate, usually inversely expressed as kh (a nd measured in wh per pulse), is determined by the ce ram registers wrate , pulse_slow , pulse_fast , in_8 , as well as by the sensor scaling vmax and imax per the equation: ] / [ 8_ 1132 .47 pulse wh x n wrate in imax vmax kh acc ? ? ? ? ? = where in_8 is the gain factor (1 or 8) controlled by the ce var iable in_shunt , x is the pulse gain factor controlled by the ce variables pulse_slow and pulse_fast n acc is the accumulation count ( pre_samps * sum_cycles ) downloaded from: http:///
71m6511/71m6511h single - phase energy meter ic data sheet november 20 10 page: 56 of 98 ? 2005 C 2010 teridian semiconductor corporation v2.7 a maxim integrated products brand program security when enabled, the security feature limits the ice to global flash erase operat ions only. all other ice operations are blocked. this guarantees the security of the users mpu and ce program code. security is enabled by mpu code that is executed in a 32 cycle preboot interval before the primary boot sequence begins. once security is enabled, the only way to disable it is to perform a global erase of the flash memory, followed by a chip re set. global flash erase also clears the ce pram. the first 32 cycles of the mpu boot code are called the preboot phase bec ause during this phase the ice is inhibited. a read - only status bit, preboot (sfr 0xb2[7]), identifies these cycles to the mpu. upon compl etion of the preboot sequence, the ice can be enabled and is permitted to take control of the mpu. secure (sfr 0xb2[6]), the security enable bit, is reset whenever the mpu is reset. hardware associated with the bit permits only ones to be written to it. thus, preboot code may set secure to enable the security feature but may not reset it. once secure is set, the preboot code is protected and no externa l read of program code is possible. specifically, when secure is set: ? the ice is limited to bulk flash erase only. ? page zero of flash memory, the preferred location for the users preboot code, may not be page - erased by either mpu or ice. page zero may only be erased with global flash erase. note that global flash erase erases ce program ram whether secure is set or not. ? writes to page zero, whether by mpu or ice, are inhibited. the secure bit is to be used with caution! inadvertently setting this bit w ill inhibit access to the part via the ice interface, if no mechanism for actively resetting the part between reset and erase operations is provided (see ice interface description). additionally, by setting the i/o ram register eck_dis to 1, the emulator c lock is disabled, inhibiting access to the program with the emulator. see the cautionary note in the i/o ram register description! downloaded from: http:///
71m6511/71m6511h single - phase energy meter ic data sheet november 20 10 page: 57 of 98 ? 2005 C 2010 teridian semiconductor corporation v2.7 a maxim integrated products brand firmware interface i/o ram map C in numerical order not used bits are blacked out and contain no memory and are read by the mpu as zero. reserved bits are in use and should not be changed. name addr bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 configuration: ce0 2000 equ[2:0] ce_en tmux[3:0] ce1 2001 pre_samps[1:0] sum_cycles[5:0] ce2 2002 mux_div[1:0] chop_en[1:0] rt m_en wd_ovf ex_rtc ex_xfr comp0 2003 reserved reserved comp_stat[0] config0 2004 vref_cal reserved ckout_dis vref_dis mpu_div config1 2005 reserved eck_dis fir_len adc_dis mux_alt flash66z mux_e version 2006 version[7:0] digital i/o: dio0 2008 opt_txdis dio_eex dio_pw dio_pv dio1 2009 reserved reserved dio2 200a reserved reserved dio3 200b dio_r5[2:0] dio_r4[2:0] dio4 200c dio_r7[2:0] dio_r6[2:0] dio5 200d dio_r9[2:0] dio_r8[2:0] dio6 200e dio_r11[2:0] dio_r10[2:0] real time clock: rtc0 2015 rtc_sec[5:0] rtc1 2016 rtc_min[5:0] rtc2 2017 rtc_hr[4:0] rtc3 2018 rtc_day[2:0] rtc4 2019 rtc_date[4:0] rtc5 201a rtc_mo[3:0] rtc6 201b rtc_yr[7:0] rtc7 201c rtc_dec_sec rtc_inc_sec lcd display interface: lcdx 2020 lcd_bsten lcd_num[4:0] lcdy 2021 lcd_en lcd_mode[2:0] lcd_clk[1:0] lcdz 2022 lcd_fs[4:0] lcd0 2030 lcd_seg0[3:0] lcd1 2031 lcd_seg1[3:0] lcd19 2043 lcd_seg19[3:0] lcd20 2044 reserved lcd23 2047 reserved lcd24 2048 lcd_seg24[3:0] lcd31 204f lcd_seg31[3:0] lcd32 2050 lcd_seg32[3:0] lcd33 2051 lcd_seg33[3:0] lcd34 2052 lcd_seg34[3:0] lcd35 2053 lcd_seg35[3:0] lcd36 2054 lcd_seg36[3:0] lcd37 2055 lcd_seg37[3:0] downloaded from: http:///
71m6511/71m6511h single - phase energy meter ic data sheet november 20 10 page: 58 of 98 ? 2005 C 2010 teridian semiconductor corporation v2.7 a maxim integrated products brand lcd38 2056 reserved lcd39 2057 reserved lcd40 2058 reserved lcd41 2059 reserved rtm probes: rtm0 2060 rtm0[7:0] rtm1 2061 rtm1[7:0] rtm2 2062 rtm2[7:0] rtm3 2063 rtm3[7:0] synchronous serial interface: ssi 2070 ssi_en ssi_10m ssi_ckgat e ssi_fsize[1:0] ssi_fpol ssi_rdyen ssi_rdypo l ssi_be g 2071 ssi_beg[7:0] ssi_end 2072 ssi_end[7:0] fuse selection registers: trimsel 20fd trimsel[7:0] trim 20ff trim[7:0] sfr map (sfrs specific to teridian 80515) C in numerical order not used bits are blacked out and contain no memory and are read by t he mpu as zero. reserved bits are in use and should not be changed. this table lists only the sfr registers that are not generic 8051 sfr registers. name sfr addr bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 digital i/o: p0 80 dio_0[7:4] (port 0) reserved dir0 a2 dio_dir0[7:4] 1111 p1 90 dio_1[7:6] (port 1) dio_1[3:0] (port 1) dir1 91 dio_dir1[7:6] dio_dir1[3:0] p2 a0 reserved dio_2[1:0] (port 2) dir2 a1 1111 dio_dir2[1:0] interrupts and wd timer: intbits f8 int6 int5 int4 int3 int2 int1 int0 wdi e8 wd_rst ie_rtc ie_xfer flash: erase 94 flsh_erase[7:0] flshctl b2 preboot secure flsh_meen flsh_pwe pgadr b7 flsh_pgadr[6:0] serial eeprom: 9e eedata[7:0] 9f eectrl[7:0] downloaded from: http:///
71m6511/71m6511h single - phase energy meter ic data sheet november 20 10 page: 59 of 98 ? 2005 C 2010 teridian semiconductor corporation v2.7 a maxim integrated products brand i/o ram (configuration ram) C alphabetical order many functions of the chip can be controlled via the i/o ram (configur ation ram). the ce will also take some of its para - meters from the i/o ram. bits with a w (write) direction are written by the mpu into i/o ram. typically, they are initially stored in flash memory and copied to the i/o ram by the mpu. some of the more frequently programmed bits ar e mapped to the mpu sfr memory space. the remaining bits are mapped to 2xxx. bits with r (read) direction can only be read by the mpu. on power up, all bits are cleared to zero unless otherwise stated. generic sfr registers are not listed. name location [bit(s)] dir description adc_dis 2005[3] r/w disables adc and removes bias current ce_en 2000[4] r/w ce enable. chop_e n[1:0] 2002[5:4] r/w chop enable for the reference band gap circuit. 00: enabled 01: disabled 10: disabled 11: enabled reserved 2004[5] r/w must be 0. ckout_dis 2004[4] r/w ckout disable. when zero, cktest is an active output. reserved 2003[4:3] r/w m ust be 0. reserved 2003[2:0] r reserved dio_r4[2:0] dio_r5[2:0] dio_r6[2:0] dio_r7[2:0] dio_r8[2:0] dio_r9[2:0] dio_r10[2:0] dio_r11[2:0] 200b[2:0] 200b[6:4] 200c[2:0] 200c[6:4] 200d[2:0] 200d[6:4] 200e[2:0] 200e[6:4] r/w r/w r/w r/w r/w r/w r/w r/w con nects dedicated i/o pins 4 to 11 to selectable internal resources. if more than one input is connected to the same resource, the multiple column below specifies how they are combined. see software users guide for details). dio_gp resource multiple 0 none -- 1 reserved or 2 t0 (counter0 clock) or 3 t1 (counter1 clock) or 4 high priority i/o interrupt (int0 rising) or 5 low priority i/o interrupt (int1 rising) or 6 high priority i/o interrupt (int0 falling) or 7 low priority i/o interrupt (int1 fal ling) or dio_dir0[7:4] sfr a2 r/w programs the direction of dio pins 7 through 4. 1 indicates output. ignored if the pin is not configured as i/o. see dio_pv and dio_pw for special option for dio6 and dio7 outputs. see dio_eex for special option for dio 4 and dio5. note: bit 0, bit 1, bit 2 and bit 3 must be set to 1. downloaded from: http:///
71m6511/71m6511h single - phase energy meter ic data sheet november 20 10 page: 60 of 98 ? 2005 C 2010 teridian semiconductor corporation v2.7 a maxim integrated products brand dio_dir1[7:6] dio_dir1[3:0] sfr91 r/w programs the direction of dio pins 15, 14 and 11 through 8. 1 indicates output. ignored if the pin is not configured as i/o. note: bit 4 and bit 5 must be set to 1. dio_dir2[1:0] sfra1[5:0] r/w programs the direction of dio pins 17 and 16. 1 indicates output. ignored if the pin is not configured as i/o. note: bit 2, bit 3, bit 4 and bit 5 must be set to 1. dio_0[7:4] dio_1[7:6], dio_1[3:0] dio_2[1 :0] sfr80 sfr90 sfr90 sfra0[1:0] r/w r/w r/w r/w port 0 port 1 port 1 port 2 the value on the dio pins. pins configured as lcd will read zero. when written, changes data on pins configured as outputs. pins configured as lcd or input will ignore writes. dio_eex 2008[4] r/w when set, converts dio4 and dio5 to interface with external eeprom. dio4 becomes sck and dio5 becomes bi - directional sda. lcd_num must be less than 18. dio_pv 2008[2] r/w causes varpulse to be output on dio7, if dio7 is configured as o utput. lcd_num must be less than 15. dio_pw 2008[3] r/w causes wpulse to be output on dio6, if dio6 is configured as output. lcd_num must be less than 17. eedata[7:0] sfr 9e r/w serial eeprom interface data eectrl[7:0] sfr 9f r/w serial eeprom interface control eck_dis 2005[5] r/w emulator clock disable. when one, the emulator clock is disabled. this bit is to be used with caution! inadvertently setting this bit will inhibit access to the part with the ice interface and thus preclude flash erase and p rogramming operations . if eck_dis is set, it should be done at least 1000ms after power - up to give emulators and programming devices enough time to complete an erase op eration. equ[2:0] 2000[7:5] r/w specifies the power equation to the ce. ex_xfr ex_rt c 2002[0] 2002[1] r/w interrupt enable bits. these bits enable the xfer_busy and the rtc_1sec interrupts to the mpu. note that if either interrupt is to be enabled, ex6 in the 80515 must also be set. fir_len 2005[4] r/w the length of the adc decimation fi r filter. 1: 22 adc bits/3 ck32 cycles (384 ckfir cycles), 0: 21 adc bits/2 ck32 cycles (288 ckfir cycles) flash66z 2005[1] r/w should be set to 1 to minimize supply current. downloaded from: http:///
71m6511/71m6511h single - phase energy meter ic data sheet november 20 10 page: 61 of 98 ? 2005 C 2010 teridian semiconductor corporation v2.7 a maxim integrated products brand flsh_erase sfr 94 w flash erase initiate flsh_erase is used to initiate eith er the flash mass erase cycle or the flash page erase cycle. specific patterns are expected for flsh_erase in order to initiate the appropriate erase cycle. (default = 0x00). 0x55 C initiate flash page erase cycle. must be proceeded by a write to flsh_pgad r @ sfr 0xb7. 0xaa C initiate flash mass erase cycle. must be proceeded by a write to flsh_meen @ sfr 0xb2 and the debug (cc) port must be enabled. any other pattern written to flsh_erase will have no effect. flsh_meen sfr b2[1] w mass erase enable 0 C ma ss erase disabled (default). 1 C mass erase enabled. must be re - written for each new mass erase cycle . flsh_pgadr sfr b7[7:1] w flash page erase address flsh_pgadr[6:0] C flash page address (page 0 thru 127) that will be erased during the page erase cycle . (default = 0x00). must be re - written for each new page erase cycle. flsh_pwe sfr b2[0] r/w program write enable 0 C movx commands refer to xram space, normal operation (default). 1 C movx @dptr,a moves a to program space ( f lash) @ dptr. this bit is aut omatically reset after each byte written to flash. writes to this bit are inhibited when interrupts are enabled. ie_xfer ie_rtc sfr e8[0] sfr e8[1] r/w interrupt flags. these flags are part of the wdi sfr register and mo - nitor the xfer_busy interrupt and the rtc_1sec inter rupt. the flags are set by hardware and must be cleared by the interrupt hand ler. see also wd_rst . intbits sfr f8[6:0] r interrupt inputs. the mpu may read these bits to see the input t o external interrupts int0, int1, up to int6. thes e bits do not have any memory and are primarily intended for debug use. lcd_bsten 2020[7] r/w enables the lcd voltage boost circuit. lcd_clk[1:0] 2021[1:0] r/w sets the lcd clock frequency for com/seg pins (not the frame rate. note: f w = ckfir/128 00: f w /2 9 , 01: f w /2 8 , 10: f w /2 7 , 11: f w /2 6 lcd_en 2021[5] r/w enables the lcd display. when disabled, vlc2, vlc1, and vlc0 are ground as are the com and seg outputs. lcd_fs[4:0] 2022[4:0] r/w controls the lcd full scale voltage, vlc2: ) 31 _ 3.0 7.0( 2 fs lcd vlcd vlc + ? = downloaded from: http:///
71m6511/71m6511h single - phase energy meter ic data sheet november 20 10 page: 62 of 98 ? 2005 C 2010 teridian semiconductor corporation v2.7 a maxim integrated products brand lcd_mode[2:0 ] 2021[4:2] r/ w the lcd bias mode. 000: 4 states, 1/3 bias 001: 3 states, 1/3 bias 010: 2 states, ? bias 011: 3 states, ? bias 100: static display lcd_num[4:0] 2020[4:0] r/ w controls the number of dual - purpose lcd/dio pins to be c onfigured as lcd. lcd_num will be between 0 and 18. the first dual - purpose pin to be allocated as lcd is seg37/dio17. the table below list s which seg and dio functions are selected for each lcd_num value. lcd_num seg dio 1-4 none dio4 - 11, dio14 - 17 5 seg3 7 dio4 - 11, dio14 - 16 6 seg36 - 37 dio4 - 11, dio14 - 15 7 seg35 - 37 dio4 - 11, dio14 8- 10 seg34 - 37 dio4 - 11 11 seg34 - 37, seg31 dio4 - 10 12 seg34 - 37, seg30 - 31 dio4 -9 13 seg34 - 37, seg29 - 31 dio4 -8 14 seg34 - 37, seg28 - 31 dio4 -7 15 seg34 - 37, seg27 - 31 dio4 -6 16 seg3 4- 37, seg26 - 31 dio4 -5 17 seg34 - 37, seg25 - 31 dio4 18 seg34 - 37, seg24 - 31 none lcd_seg0[3:0]- lcd_seg19[3:0], lcd_seg24[3:0]- lcd_seg31[3:0], lcd_seg34[3:0]- lcd_seg37[3:0], 2030[3:0] - 2043[3:0] , 2048[3:0] - 204f[3:0], 2052[3:0] - 2055[3:0] r/ w lcd segment data. each word contains information for from 1 to 4 time divisions of each segment. in each word, bit 0 corresponds to com0, on up to bit 3 for com3. mpu_div[2:0] 2004[2:0] r/ w the mpu clock divider (from ckce). these bits may be program med by the mpu withou t risk of losing control. 000 - ckce, 001 - ckce/2, , 111 - ckce/2 7 mpu_div is 000 on power - up. mux_alt 2005[2] r/ w the mpu asserts this bit when it wishes the mux to perform a dc conversions on an alternate set of inputs. mux_div[1:0] 2002[7:6] r/ w the number of states in the input multiplexer. 00 - 6 states 01 - 4 states 10 - 3 states 11 - 2 states mux_e 2005[0] r/ mux_sync enable. when high, converts seg7 into a mux_sync downloaded from: http:///
71m6511/71m6511h single - phase energy meter ic data sheet november 20 10 page: 63 of 98 ? 2005 C 2010 teridian semiconductor corporation v2.7 a maxim integrated products brand w output. opt_txdis 2008[5] r/ w tristates the opt_tx output. preboot sfr b2[7] r indicates that the preboot sequence is active. pre_samps[1:0] 2001[7:6] r/ w together w/ sum_cycles, this value determines the number of samples in one sum cycle between xfer interrupts for the ce. number of samples = pre_samps*sum_cycles . 00 - 42, 01 - 50, 10 - 84, 11 - 100 rtc_sec[5:0] rtc_mini[5:0] rtc_hr[4:0] rtc_day[2:0] rtc_date[4:0] rtc_mo[3:0] rtc_yr[7:0] 2015 2016 2017 2018 2019 201a 201b r/w the rtc interface. these are the year, month, day, hour, minute and second parameters for the rtc. the rtc is set by writing to these registers. year 00 is defined as a leap year. sec 00 to 59 min 00 to 59 hr 00 to 23 (00=midnight) day 01 to 07 (01=sunday) date 01 to 31 mo 01 to 12 yr 00 to 256 rtc_dec_sec rtc_inc_sec 201c[1] 201c[0] w rtc time correction bits. only one bit may be pulsed at a time. when pulsed, causes the rtc time value to be incremented (or decremented) by an additional second the next time the rtc_sec register is clocked. the pulse width may be any value. if an additi o nal correction is desired, the mpu must wait 2 seconds before pulsing one of the bits again. rtm_en 2002[3] r/w real time monitor enable. when 0, the rtm output is low. this b it enables the two wire version of rtm rtm0[7:0] rtm1[7:0] rtm2[7:0] rtm3[7: 0] 2060 2061 2062 2063 r/w r/w r/w r/w four rtm probes. before each ce code pass, the values of these registers are serially output on the rtm pin. the rtm registers are ignored when rtm_en =0. secure sfr b2[6] r/w enables security provisions that prevent external reading of flash memory and ce program ram. this bit is reset on chip reset and may only be set. attempts to write zero are ignored. ssi_en 2070[7] r/w enables the synchronous serial interface (ssi) on seg3, seg4, and seg5 pins. if ssi_rdyen is s et, seg6 is enabled also. the pins take on the new functions sclk, ssdata, sfr, and srdy, respectively. when ssi_en is high and lcd_en is low, these pins are converted to the ssi function, regardless of lcden and lcd_num . for proper lcd operation, ssi_en m ust not be high when lcd_en is high. ssi_10m 2070[6] r/w ssi clock speed: 0: 5mhz, 1: 10mhz ssi_ckgate 2070[5] r/w ssi gated clock enable. when low, the sclk is continuous. when high, the clock is held low when data is not being transferred. ssi_fsize [1:0] 2070[4:3] r/w ssi frame pulse format: 0: once at beginning of ssi sequence (whole block of data), 1: every 8 bits, 2: every 16 bits, 3: every 32 bits. ssi_fpol 2070[2] r/w sfr pulse polarity: 0: positive, 1: negative downloaded from: http:///
71m6511/71m6511h single - phase energy meter ic data sheet november 20 10 page: 64 of 98 ? 2005 C 2010 teridian semiconductor corporation v2.7 a maxim integrated products brand ssi_rdyen 2070[1] r/w srdy ena ble. if ssi_rdyen and ssi_en are high, the seg6 pin is configured as srdy. otherwise, it is an lcd driver. ssi_rdypol 2070[0] r/w srdy polarity: 0: positive, 1: negative ssi_beg[7:0] ssi_end[7:0] 2071[7:0] 2072[7:0] r/w the beginning and ending addr ess of the transfer region of the ce data memory. if the ssi is enabled, a block of words starting wi th ssi_beg and ending with ssi_end will be sent. ssi_end must be larger than ssi_beg . the maximum number of output words is limited by the number of ssi cl ocks in a ce code pass see fir_len, mux_div, and ssi_10m . sum_cycles [5:0] 2001[5:0] r/w together w/ pre_samps , this value determines (for the ce) the number of samples in one sum cycle between xfer interrupts. number of samples = pre_samps*sum_cycles. tmux[3:0] 2000[3:0] r/w selects one of 16 inputs for tmuxout. 0 C dgnd (analog) 1 C ibias (analog) 2 C pll_2.5v (analog) 3 C vbias (analog) 4 C rtm (real time output from ce) 5 C wdtr_en (comparator 1 output and v1lt3) 6 C reserved 7 C reserved 8 C rxd (fr om optical interface) 9 C mux_sync (from mux_ctrl) a C ck_10m b C ck_mpu c C reserved for production test d C rtclk e C ce_busy f C xfer_busy reserved 2005[7] r/w must be zero. trimsel 20fd w selects the temperature trim fuse to be read with the trim register ( trimm[2:0] : 4, trimbga : 5, trimbgb : 6) trim 20ff r contains trimbga , trimbgb , or trimm[2:0] depending on the value written to trimsel . if trimbgb = 0 then the ic is a 6511 else the ic is a 6511h. version[7:0] 2006 r the silicon revision number. this data sheet does not apply to revisions < 000 0100. vref_cal 2004[7] r/w brings vref out to the vref pin. this feature is disabled when vref_dis =1. vref_dis 2004[3] r/w disables the internal voltage reference. wd_rst sfr e8[7] w resets the wd timer . the wdt is reset when a 1 is written to this bit. only byte operations on the whole wdi register should be used. wd_ovf 2002[2] r/w the wd overflow status bit. this bit is set when the wd tim er overflows. it is powered by the vbat pin and at boot - up wil l indicate if the part is recovering from a wd overflow or a power fault. th is bit should be cleared by the mpu on boot - up. it is also automatically cleared when resetz is low. downloaded from: http:///
71m6511/71m6511h single - phase energy meter ic data sheet november 20 10 page: 65 of 98 ? 2005 C 2010 teridian semiconductor corporation v2.7 a maxim integrated products brand ce program and environment ce program the ce program is supplied by teridian as a data image that can be merged with the mpu operational code for meter applications. typically, the ce program covers most applications and does no t need to be modified. the description in this section applies to ce code revision ce11b05. formats all ce words are 4 bytes. unless specified otherwise, they are in 32 - bit twos complement ( - 1 = 0xffffffff). calibration para meters are defined in flash memory (or external eeprom) and must be copie d to ce memory by the mpu before enabling the ce. internal variables are used in internal ce calculations. in put variables allow the mpu to control the behavior of the ce code. output variables are outputs of the ce calculations. the c orresponding mpu address for the most signi ficant byte is given by 0x1000 + 4 x ce_address and 0x1003 + 4 x ce_address for the least signific ant byte. constants constants used in the ce data memory tables are: ? sampling frequency: f s = 32768hz/13 = 2520.62hz ( mux_div = 1) or 32786/10 = 3276.8hz ( mux_div = 2) ? f 0 is the fundamenta l signal frequency, typically 50 or 60hz. ? imax is the external rms current corresponding to 250mv peak at the inputs ia or ib . ? vmax is the external rms voltage corresponding to 250mv peak at the input va. ? n acc , the accumulation count for energy measuremen ts is pre_samps*sum_cycles . this value resides in sum_pre (ce address 36). ? accumulation count time for energy measurements is pre_samps*sum_cycles /f s . ? in_8 is a gain constant of current channel n. its value is 8 or 1 and is controlled by in_shunt . ? x is a gain constant of the pulse generators. its value is determi ned by pulse_fast and pulse_slow . ? voltage lsb = vmax * 3.3243*10 - 9 v (peak). the system constants imax and vmax are used by the mpu to convert internal digital quantities (as used by the ce) to ext ernal, i.e. metering quantities. their values are determined by the scali ng of the voltage and current sensors used in an actual meter. the lsb values used in this document relate digital quan tities at the ce or mpu interface to external meter inp ut quanti ties. for exam ple, if a sag threshold of 80v peak is desired at the meter input, the digita l value that should be pro - grammed into sag_thr would be 80v/ sag_thr lsb , where sag_thr lsb is the lsb value in the description of sag_thr . the parameters equ , ce_en , pre_samps, and sum_cycles are essential to the function of the ce and are stored in i/o ram (see i/o ram section). downloaded from: http:///
71m6511/71m6511h single - phase energy meter ic data sheet november 20 10 page: 66 of 98 ? 2005 C 2010 teridian semiconductor corporation v2.7 a maxim integrated products brand environment before starting the ce using the ce_en bit, the mpu has to establish the proper environment for the ce by implementing the foll owing steps: ? loading the image for the ce code into ce pram. ? loading the ce data into ce dram. ? establishing the equation to be applied in equ . ? establishing the accumulation period and number of samples in pre_samps and sum_cycles. ? establishing the number of cycles per adc mux cycle. the default configuration is fir_len = 1 (three cycles per conversion) and mux_div = 1 (4 conversions per mux cycle). there must be thirteen ck32 cycles (see system timing diagram, figure 13 ). this mea ns that the product of the number of cycles per adc conversion and the number of conversions per cycle must be 12 (allowing for one settling cycle). alternatively, the 71m6511 can be operated at ten ck32 cycles per adc mux cycle ( mux_div = 2). ce quantiti es are stated in this section for mux_div = 2, if they differ from those associated with the default setti ng. during operation, the mpu is in charge of controlling the multiplexer cycl es, for example by inserting an alternate multiplex er sequence at regula r intervals using mux_alt . this enables temperature measurement. the polarity of chop must be altered for each sample. it must also alternate for each alternate multi plexer reading. the mpu must program chop_en alternately between 01 and 10 on every ce_busy interrupt except for the first ce_busy after an xfer_busy interrupt. note that when xfer_busy occurs, i t will always be at the same time as a ce_busy interrupt. operating ce codes with environment parameters deviating from the val ues specified by teridi an will lead to unpredictable results. ce calculations the ce performs the precision computations necessary to accuratel y measure power. these computations include offset cancellation, phase compensation, product smoothing, product summation, freque ncy d etection, var calculation, sag detection, peak detection, and voltage phase measurement. all data computed by the c e is dependent on the selected meter equation as given by equ ( in i/o ram ) . as a function of equ , the element components v0 through i2 take on different meanings. ? equ watt & var formula (wsum/varsum) element input mapping w0sum/ var0sum w1sum/ var1sum i0sqsum i1sqsum 0 va ia (1 element, 2w 1 ) va*ia va*ib ia ib 1 va*(ia - ib)/2 (1 element, 3w 1 ) va*(ia - ib)/2 va*ib ia - ib ib downloaded from: http:///
71m6511/71m6511h single - phase energy meter ic data sheet november 20 10 page: 67 of 98 ? 2005 C 2010 teridian semiconductor corporation v2.7 a maxim integrated products brand ce ram locati ons ce front end data (raw data) access to the raw data provided by the afe is possible by reading addresses 0 through 7, as listed below. address (hex) name description 00 ia phase a current 01 va phase a voltage 02 ib phase b current 03 - reserved 04 - reserved 05 - reserved 06 temp temperature 07 -- reserved ce status word since the ce_busy interrupt occurs at 2520.6hz (or at 3276.8hz when mux_div = 2), it is desirable to minimize the computation required in the inter rupt handler of the mpu. the mpu can read cestatus at every ce_busy interrupt. ce address name description 0x51 cestatus see description of ce status word below the ce status word is useful for generating early warnings to the mpu. it contains sag warnings for phase a, as we ll as f0, the derived clock operating at the fundamental input frequency. cestatus provides information about the status of voltage and input ac signal frequency, which are useful for generating an early power fail warning to ini tiate necessary data storag e. cestatus represents the status flags for the preceding ce code pass (ce_busy i nterrupt). note: the ce does not store sag alarms from one code pass to the ne xt. cestatus is refreshed at every ce_busy inter rupt and remains valid for up to 100s after the ce_busy interrupt occurs. unsynchronized read operations of cestatus will yield unreliable results. the significance of the bits in cestatus is shown in the table below: cestatus [bit] name description 31 - 29 not used these unused bits will always be zero . 28 f0 f0 is a square wave at the exact fundamental input frequency. 27 reserved 26 reserved 25 sag_a normally zero. becomes one when va remains below sag_thr for sag_cnt samples. will not return to zero until va rises above sag_thr . 24 -0 not used these unused bits will always be zero. downloaded from: http:///
71m6511/71m6511h single - phase energy meter ic data sheet november 20 10 page: 68 of 98 ? 2005 C 2010 teridian semiconductor corporation v2.7 a maxim integrated products brand for generating proper status information, the ce is initialized by the mpu using sag_thr (default of 80v rms at the meter input if vmax =600v) and sag_cnt (default 80 samples). using the default value for sag_cnt , th e peak - to - peak signal has to be below sag_thr value for 32 milliseconds to activate the sag_x status bits. ce address name default description 0x31 sag_thr +56,722,300 (0x361837c) meter voltage inputs must be above this threshold to prevent sag alar ms. l sb = vmax * 3.3243*10 - 9 v peak. for example, if a sag threshold of 80v rms is desired, 9 10 3243 .3 2 80 _ ? ? ? = vmax thr sag 0x32 sa g_ c nt 80 number of consecutive voltage samples below sag_thr before a sag alarm is declared. 80*397s = 31.8ms (for mux_div = 1). ce transfer variables when the mpu receives the xfer_busy interrupt, it knows that fresh data is avail able in the transfer variables. ce trans fer variables are modified during the ce code pass that ends with an xfer_bus y interrupt. they remain constant throu ghout each accumulation interval. in this data sheet, the names of ce tr ansfer variables always end with _x. fundamental power measurement variables the table below describes each transfer variable for fundamental power measurement. all variables are signe d 32 bit integers. accumulated variables such as wsum are internally scaled so they have at le ast 2x margin before overflow when the integration time is 1 second. additionally, the hardware will not per mit output values to fold back upon overflow. ce ad dress name description 42 reserved 43 w0sum_x the sum of watt samples from each wattmeter element ( in_8 is the gain configured by ia_shunt or ib_shunt ). lsb = 6.6952*10 - 13 vmax imax / in_8 wh (for mux_div = 1) lsb = 5.1501*10 - 13 vmax imax / in_8 wh (for mux_div = 2) 44 w1sum_x 45 reserved 46 reserved 47 var0sum_x the sum of var samples from each wattmeter element ( in_8 is the gain configured by ia_shunt or ib_shunt ). lsb = 6.6952*10 - 13 vmax imax / in_8 wh (for mux_div = 1) lsb = 5.1501*10 - 13 vmax imax / in_8 wh (for mux_div = 2) 48 var1sum_x 49 reserved wxsum_x is the wh value accumulated for element x in the last accumulation interval and can be computed based on the specified lsb value. for example with vmax = 600v and imax = 208a, lsb ( for wxsum_x ) is 0.08356 wh ( mux_div = 1). downloaded from: http:///
71m6511/71m6511h single - phase energy meter ic data sheet november 20 10 page: 69 of 98 ? 2005 C 2010 teridian semiconductor corporation v2.7 a maxim integrated products brand instantaneous power measurement variables the freqsel register selects the input phase used for frequency measurement and for the main_edge counter. the frequency measurement is implemented using the frequenc y locked loop of the ce for the selected phase. ixsqsum_x and vxsqsum are the squared current and voltage samples acquired during the last accumulation interv al. insqsum_x can be used for computing the neutral current. ce address name description 33 r eserved 41 freq_x fundamental frequency. lsb 6 32 10 587 .0 2 ? ? s f hz for mux_div = 1 or 6 32 10 763 .0 2 ? ? s f hz for mux_div = 2 4a i0sqsum_x the sum of squared current samples from each element. lsb = 6.6952*10 - 13 imax 2 / in_8 2 a 2 h (for mux_div = 1) lsb = 5.1501*10 - 13 imax 2 / in_8 2 a 2 h ( for mux_div = 2) 4b i1sqsum_x 4c reserved 4d reserved 4e v0sqsum_x the sum of squared voltage samples from each element. lsb= 6.6952*10 - 13 vmax 2 v 2 h (for mux_div = 1) lsb = 5.1501*10 - 13 vmax 2 v 2 h ( for mux_div = 2) 4f reserved 50 reserved the rms values can be computed by the mpu from the squared current and voltage samples as per the formulae: note: fs = 2520.6hz ( mux_div = 1) or 3276.8hz ( mux_div = 2) other measurement parameters mainedge_x is useful for implementing a real - time clock based on the input ac signal. mainedge_x is the number of half - cycles accounted for in the last accumulated interval for the a c signal of the phase specified in the freqsel register. ce address name description 52 re served 53 reserved 55 mainedge_x the number of edge crossings of the selected voltage in the pre vious accumulation interval. edge crossings are either direction and ar e de - bounced. acc s rms n f lsb vxsqsum vx ? ? ? = 3600 acc s rms n f lsb ixsqsum ix ? ? ? = 3600 downloaded from: http:///
71m6511/71m6511h single - phase energy meter ic data sheet november 20 10 page: 70 of 98 ? 2005 C 2010 teridian semiconductor corporation v2.7 a maxim integrated products brand temperature measurement and temperature compensation input variable s: temp_nom is the reference value for temperature measurement, i.e. when this val ue is set with temp_raw_x at known temperature. the 71m6511/6511h measures temperature with ref erence to this value. degscale is the slope or rate of temperature increase or decrease from the temp_nom for temp_x measurement. ppmc and ppmc2 are temperature compensation coefficients. their values should reflect the characteristics of the band gap voltage reference of the chip. ppmc and ppmc2 follow the square law characteristics to compensate for nonlinear temperature behaviors, when the 71m6511/6511h is in internal temperature compensation m ode. ce addres s name defaul t description 0x11 temp_nom 0 during calibration, the value of temp_raw_x should be placed in temp_nom . 0 x30 degscale 9585 scale factor for temp_x . temp_x = - degscale *2 - 22 *( temp_raw_x - temp_nom ). 0x38 ext_temp 0 should be 15 or 0. when 15, causes the ce to ignore internal tem - perature compensation and permits the mpu to control gain_adj . when internal temper ature compensation is selected, gain_adj will be: ? ?? ? ? ?? ? ? + ? + + = 23 2 14 2 2 _ 2 _ 1 16384 _ ppmc x temp ppmc x temp floor adj gain default is 0 (internal compensation). 0x39 ppmc 0 linear temperature com pensation factor. equals the linear temperature co efficient (ppm/c) of vref multiplied by 26.84, or tc1 (exp ressed in v/c, see electrical specifications) multiplied by 22.46. a positive value will cause the meter to run faster when hot. the compensati on factor affects both v and i and will therefore have a double effec t on products. 0x3a ppmc 2 0 square - law temperature compensation factor. equals the square - law tem perature coefficient (ppm/c 2 ) of vref multiplied by 1374, or tc2 (ex pressed in v/c 2 , see electrical specifications) multiplied by 1150.1 . a po sitive value will cause the meter to run faster wh en hot. the compensa tion factor affects both v and i and will therefore have a double effect on prod ucts. ext_temp allows the mpu to select between direct control of gain_adj or management of gain_adj by the ce, based on temp_x and the temperature correction coefficients ppmc and ppmc2 . output variables: temp_x is the temperature measurement from reference temperature of temp_nom . temp_x is computed using temp_raw_x and degscale . this quantity is positive when the temperature is above the reference and is negative for cold temperatures. temp_raw_x is the raw processed value from adc output and is the fundamental quantity for tem perature measurement. temp_raw_x is less than temp_nom at higher temperatures. temp_raw_x is more than temp_nom for cooler tempe ratures than reference temperature. downloaded from: http:///
71m6511/71m6511h single - phase energy meter ic data sheet november 20 10 page: 71 of 98 ? 2005 C 2010 teridian semiconductor corporation v2.7 a maxim integrated products brand gain_adj is a scaling factor for power measurements based on temperature (when in internal temperature compensation mode). in general, for higher temperatures it is lower than 16384 and higher than 16384 for lower tempe ratures. gain_adj is mainly dependent on the ppmc , ppmc2 and temp_x register values. this parameter is automatically computed by the ce and is used by the ce for temperature compensation. ce address name description 0x40 temp_x deviation from calibration temperature. lsb = 0.1 0 c. 0x54 temp_raw_x filtered, unscaled reading from temperature sensor. this value should be written to temp_nom during meter calibration. 0x2e gain_adj scales all voltage and current inputs. 16384 provides unity gain. default is 1 6384 . if ext_tmp = 0, gain_adj is updated by the ce. pulse generation input variables: the combination of the pulse_slow and pulse_fast parameters control the speed of the pulse rate. the default values of 1 and 1 will maintain the original pulse rate gi ven by the kh equation. wrate controls the number of pulses that are generated per measured wh and varh quantities. the lower wrate it is the slower is the pulse rate for measured power quantity. the metering constant k h is derived from wrate as the amount of energy measured for each pulse. that is, if kh = 1wh/pulse, a power applied to the meter of 120v and 30a results in one pulse per second. if the load is 240v at 150a, ten pulses per second wil l be generated. control is transferred to the mpu for pulse generation if ext_pulse > 0. in this case, the pulse rate is determined by apulsew and apulser . the mpu has to load the source for pulse generation in apulsew and apulser to generate pulses. irrespective of the ext_pulse, status the output pulse rate controlled by apulsew and apulser is implemented by the ce only. by setting ext_pulse > 0, the mpu is providing the source for pulse generation. if ext_pulse is negative, w0sum_x and var0sum_x are the default pulse generation sources. in this case, creep cannot be controlled since it is an mpu function. the maximum pulse rate is f s /2= 1260.3hz ( mux_div = 1). pulse_width allows adjustment of the pulse width for compatibility with c alibration and other external equipment. when mux_div = 1, the minimum pulse widt h possible is 397s. the maximum time jitter is 397s (for mux_div = 1) and is independent of the number of pulses measured. thus, if the pulse generator is monitored for 1 second, the peak jitter is 397ppm. aft er 10 seconds, the peak jitter is 39.7ppm. t he average jitter is always zero. if it is attempted to drive either pulse generator faster than its maximum rate, it will simply output at its maximum rate without exhibiting any roll - over characteristics. the actual pulse rate, using wsum as an example, is: hz f wsum wrate x rate s 46 2 ? ? ? = where f s = 2520.6hz (sampling frequency for mux_div = 1) or 3276.8hz (sampling frequency for mux_div = 2) and x is the pulse gain factor derived from ce variables pulse_slow and pulse_fast (see table below). downloaded from: http:///
71m6511/71m6511h single - phase energy meter ic data sheet november 20 10 page: 72 of 98 ? 2005 C 2010 teridian semiconductor corporation v2.7 a maxim integrated products brand ce address name de fault description 0x28 pulse_slow 1 when pulse_slow > 0, the pulse generator input is reduced 64x. when pulse_fast > 0, the pulse generator input is increased 16x. these two parameters control the pulse gain factor x (see table below ). allowed values are either 1 or C 1. x pulse_slow pulse_fast 1.5 * 2 2 = 6 - 1 - 1 1.5 * 2 6 = 96 -1 1 1.5 * 2 - 4 = 0.09375 1 -1 1.5 1 (default) 1 (default) 0x29 pulse_fast 1 0x2d wrate 1556 kh = vmax * imax *47.1132 / ( in_8 * wrate *n acc *x) wh/pulse (for mux_div = 1 ) . vmax * imax *36.2409 / ( in_8 * wrate *n acc *x) wh/pulse (for mux_div = 2) . 0x36 sum_pre 2520 pre_samps * sum_cycles. this variable is also called n acc . 0x37 ext_pulse 15 should be 15 or 0. when zero, causes the pulse generators to respond to wsum_x and varsu m_x . otherwise, the generators respond to values the mpu places in apulsew and apulser . 0x3c pulse_width 50 the maximum pulse width (low - going pulse) is: (2 * pulse_width + 1) * 397s (for mux_div = 1) (2 * pulse_width + 1) * 305s (for mux_div = 2) 0 is a legitimate value. 0x26 apulsew 0 wh pulse generator input, to be updated by the mpu when using external pulse generation (see dio_pw bit). the output pulse rate is: apulsew * f s * 2 - 32 * wrate * 2 - 14 this input is buffered and can be updated by the mpu during a computation in - terval. the change will take effect at the beginning of the next i nterval. 0x27 apulser 0 varh pulse generator input to be updated by the mpu when using external pulse generation (see dio_pv bit). the output pulse rate is: apulser * f s *2 - 32 * wrate * 2 - 14 this input is buffered and can be updated by the mpu during a computation in - terval. the change will take effect at the beginning of the next i nterval. downloaded from: http:///
71m6511/71m6511h single - phase energy meter ic data sheet november 20 10 page: 73 of 98 ? 2005 C 2010 teridian semiconductor corporation v2.7 a maxim integrated products brand s f f t f 0 0 = current shunt variables input variables : ia_shunt and ib_shunt can configure the current inputs to accept shunt resistor sensors. in this c ase the ce provides an additional gain of 8 to the current inputs. this will enable the pulse rate to change by 8 times. in order to maintain a normal pulse rate wrate may have to be decreased by 8 times. whenever ia_shunt or ib_shunt are set to 1 or a positive number, in_8 is assigned a value of 8 in the equation for kh. ce address name default description 2a ia_shunt -1 when +1, these variables increase the respective current gain by 8. the gain factor controlled by in_shunt is referred to as in_8 throughout this document. allowed values are 1 or C 1. for example, if ib_shunt =- 1, ib_8 = 1, if ib_shunt = 1, ib_8 = 8. ia_shunt corresponds to ia_8 , ib_shunt corresponds to ib_8 . 2b ib_shunt -1 2c reserved ce calibration parameters the table below lists the parameters that are typically entered to affect calibration of meter accuracy. ce address name default description 8 cal_ia 16384 these constants control the gain of their respective channels. the nomi nal value for each parameters is 2 14 = 16384. the gain of each channel is directly proportional to its cal parameter. thus, if the gain of a channel is 1 % slow, cal should be scaled by 1/(1 C 0.01). 9 cal_va 16384 a cal_ib 16384 b reserved c reserved d reserved e phadj_a 0 these two constants control the ct phase compensation. no com pensation occurs when phadj_x = 0. as phadj_x is increased, more compensation (lag) is introduced. range: 2 15 C 1. if it is desired to delay the c urrent by the angle : ? ? ? = tan c b tan a x phadj 20 2 _ ) 2 cos( ) 2 1(2 ) 2 1( 1 0 9 29 t f a ? ? ? ? ? + = ) 2 sin( ) 2 1( 0 9 t f b ? ? = ) 2 cos( ) 2 1( 1 0 9 t f c ? ? ? = f 0 10 0 downloaded from: http:///
71m6511/71m6511h single - phase energy meter ic data sheet november 20 10 page: 74 of 98 ? 2005 C 2010 teridian semiconductor corporation v2.7 a maxim integrated products brand other ce parameters the table below shows ce parameters used for suppression of noise due to scaling a nd tr uncation effects as well as scaling factors. ce address name default description 2f 22 quanta quantb 0 0 these parameters are added to the watt calculation to compensate fo r in put noise and truncation. lsb=( vmax * imax / ia_8 ) *7.4162*10 - 10 w for phase a, and lsb=( vmax * imax / ib_8 ) *7.4162*10 - 10 w for phase b 34 24 quant_vara quant_varb 0 0 these parameters are added to the var calculation to compensate for in put noise and truncation. lsb = ( vmax * imax / ia_8 ) * 7.4162*10 - 10 w for phase a, and lsb = ( vmax * imax / ib_8 ) * 7.4162*10 - 10 w for phase b 35 23 quant_ia quant_ib 0 0 these parameters are added to compensate for input noise and truncati on in the squaring calculations for i 2 and v 2 . lsb= vmax 2 *7.4162*10 - 10 v 2 , lsb= ( imax 2 /ia_8 2 )*7.4162*10 - 10 a 2 for phase a and lsb= ( imax 2 /ib_8 2 )*7.4162*10 - 10 a 2 for phase b. 3b kvar 6448 12880 scale factor for the var calculation. the default value of kvar should never need to be changed. for mux_div = 1 for mux_div = 2 downloaded from: http:///
71m6511/71m6511h single - phase energy meter ic data sheet november 20 10 page: 75 of 98 ? 2005 C 2010 teridian semiconductor corporation v2.7 a maxim integrated products brand typical performance data wh accuracy at roo m temperature figure 24 : wh accuracy, 0.3a - 200a/240v varh accuracy at room temperature figure 25 : varh accuracy for 0.3a to 200a/240v performance downloaded from: http:///
71m6511/71m6511h single - phase energy meter ic data sheet november 20 10 page: 76 of 98 ? 2005 C 2010 teridian semiconductor corporation v2.7 a maxim integrated products brand harmonic performance -8 -7 -6 -5 -4 -3 -2 -1 0 1 2 1 3 5 7 9 11 13 15 17 19 21 23 25 harmonic error [%] 50hz harmonic data 60hz harmonic data test performed at current distortion amplitude of 40% and voltage distortion amplit ude of 10% as per iec 62053, part 2 2. figure 26 : meter accuracy over harmonics at 240v, 30a downloaded from: http:///
71m6511/71m6511h single - phase energy meter ic data sheet november 20 10 page: 77 of 98 ? 2005 C 2010 teridian semiconductor corporation v2.7 a maxim integrated products brand application informat ion connection of sensors (ct, resistive shunt, rogowski coil) figure 27 and figure 28 show how resistive dividers, current transformers, restive shunts, and rogowski coils are connected to the voltage and current inputs of the 71m6511. the analog input pins of the 7 1m6511 are designed for sensors with low source impedance. rc filters with resistance values higher than those implemented in the teridian de mo boards should be avoided. va = vin * r out /(r out + r in ) v in r in r out va figure 27 : resistive voltage divider (left), current transformer (right) figure 28 : resistive shunt (left), rogowski coil (right) distinction between 71m6511 and 71m6511h parts 71m6511h parts go through a process of trimming and characterization during production that make them suitable to high - accuracy applications. the first process applied to the 71m6511h is the trimming of the r eference voltage, which is guaranteed to have accuracy over temperature of better that 10ppm/c. the second process applied to the 71m6511h is the characterization of the reference voltage ove r temperature. the coefficients for the reference voltage are stored in so - called trim fuses (i/o r am registers trimbga , trimbgb , trimm[2:0]. the mpu program can read these trim fuses and calculate the correc tion coefficients ppm1 and ppm2 per the formulae given in the performance specifications section (vref, vbias). s ee the temperature compensation section for details. the fuse trimbgb is non - zero for the 71m6511h part and zero for the 71m6511 part. trim fuse information is not available for non - h parts. thus, the standard are to be applied. these settings are: ? ppmc = tc1 * 22.46 = C 149 ? ppmc2 = tc2 * 1 150.1 = C 392 vout = di in / dt v out r 1/n i in v c v3p3 ia vout = di in / dt v out r downloaded from: http:///
71m6511/71m6511h single - phase energy meter ic data sheet november 20 10 page: 78 of 98 ? 2005 C 2010 teridian semiconductor corporation v2.7 a maxim integrated products brand temperature compensation and mains frequency stabilization for the rtc the accuracy of the rtc depends on the stability of the external crysta l. crystals vary in terms of initial accuracy as well as i n terms of behavior over temperature. the flexibility provided by t he mpu allows for compensation of the rtc using the sub - strate temperature. to achieve this, the crystal has to be char acterized over temperature and the three coefficients y_cal , y_calc , and y_cal_c2 have to be calculated. provided the ic substrate temperatures tracks the crystal temperature, th e coefficients can be used in the mpu firmware to trigger occasional corrections of the rtc seconds count, using the rtc_dec_sec or rtc_inc_sec registers in i/o ram. it is not recommended to measure crystal frequency directly due to the error i ntroduced by the measurement probes. a practical method to measure the crystal frequency (when installed on the pcb wit h the 71m6511) is to have a dio pin toggle every second, based on the rtc interrupt, with all other interrupts disabled. when this signal is measured with a precision timer, the crystal frequency can be obtained from the measured tim e period t (in s): t s f 6 10 32768 = example: let us assume a crystal characterized by the measuremen ts shown in table 62 . the values show that even at nominal temperature (the temperature at which the chip was calibrated for ene rgy), the de viation from the ideal crystal frequency is 11.6 ppm, resulting in about one second inacc uracy per day, i.e. more than some standards allow. deviation from nominal temperature [c] measured frequency [hz] deviation from nominal frequency [ppm] +50 32767.98 - 0.61 +25 32768.28 8.545 0 32768.38 11.597 - 25 32768.08 2.441 - 50 32767.58 - 12.817 table 62 : frequency over temperature as figure 29 shows, even a constant compensation would not bring much improvement, since the temperature characteristics of the crystal are a mix of constant, linear, and quadratic effec ts (in commercially available crystals, the constant and quadrati c effects are dominant). 32767.5 32767.6 32767.7 32767.8 32767.9 32768 32768.1 32768.2 32768.3 32768.4 32768.5 -50 -25 0 25 50 figure 29 : crystal frequency over temperature the temperature characteristics of the crystal are obtained from the curve in figure 29 by curve - fitting the ppm deviations. a fairly close curve fit is achieved with the coefficients a = 10 .89, b = 0.122, and c = C 0.00714 (see figure 30 ). downloaded from: http:///
71m6511/71m6511h single - phase energy meter ic data sheet november 20 10 page: 79 of 98 ? 2005 C 2010 teridian semiconductor corporation v2.7 a maxim integrated products brand when applying the inverted coefficients, a curve (see figure 30 ) will result that effectively neutralizes the original crysta l characteristics. the frequencies were calculated using the fit c oefficients as follows: ? ? ? ? ? ? + + + ? = 6 2 6 6 10 10 10 1 c t b t a f f nom 32767.5 32767.6 32767.7 32767.8 32767.9 32768 32768.1 32768.2 32768.3 32768.4 32768.5 -50 -25 0 25 50 crystal curve fit inverse curve figure 30 : crystal compensation the mpu demo code supplied with the teridian demo kits has a direct interf ace for these coefficients and it directly con - trols the rtc_dec_sec or rtc_inc_sec registers. the demo code uses the coe fficients in the following form: 1000 2 _ 100 _ 10 _ ) ( 2 calc y t calc y t cal y ppm correction ? + ? + = note that the coefficients are scaled by 10, 100, and 1000 to provide more resolut ion. for our example case, the coefficients would then become (after rounding, since the demo code accepts only intege rs): y_cal = 109, y_calc = 12, y_calc2 = 7 alternatively, the mains frequency may be used to stabilize or check the f unction of the rtc. for this purpose, the ce provides a count of the zero crossings detected for the selected line voltage in the main_edg e_x address. this count is equivalent to twice the line frequency, and can be used to synchroniz e and/or correct the rtc. external temperature compensation in a production electricity meter, the 71m6511 or 71m6511h is not the only component contr ibuting to temperature de - pendency. in fact, a whole range of components (e.g. current transformers, r esistor dividers, power sources, filter capacitor s) will exhibit slight or pronounced temperature effects. since the output of the on - chip temperature sensor is acc essible to the mpu, temperature - compensation mechanisms with great flexibility, i.e. beyond the capabili ties implemented in the ce, are possible. temperature measurement temperature measurement can be implemented with the following steps: 1) at a known temper ature t n , read the temp_raw register of the ce and write the value into temp_nom . 2) read the temp_x register at the known temperature. the obtained value should be < 0.1c. 3) the temperature t (in c) at any environment can be obtained by r eading temp_x and ap plying the following formula: 10 _ x temp t t n + = downloaded from: http:///
71m6511/71m6511h single - phase energy meter ic data sheet november 20 10 page: 80 of 98 ? 2005 C 2010 teridian semiconductor corporation v2.7 a maxim integrated products brand crystal oscillator the oscillator drives a standard 32.768 khz watch crystal. the osci llator has been designed specifically to handle these crystals and is compatible with their high impedance and lim ited power handling capability . the oscillator power dissipation is very low to maximize the lifetime of any battery backup devic e attached to vbat. board layouts with minimum capacitance from xin to xout will require less battery current. good layouts will have xin and xout shielded from each other. for best rejection of electromagnetic interference, connect the crystal body and the ground terminals of the two crystal capacitors to gndd through a ferrite bead. no external r esistor should be connected a cross the crystal, since the oscillator is self - biasing. connecting lcds the 71m6511 has a lcd controller on - chip capable of controlling static or multiplexed lcds. figure 31 shows the basic connection for a lcd. segments 71m6511 lcd commons segments 71m6511 lcd commons figure 31 : connecting lcds figure 32 shows how 5v lcds can be operated even when a 5v supply is not available. setting the i/o ram re gister lcd_bsten to 1 starts the on - chip boost circuitry that will output an ac frequency on the vdrv pin. using a small cou pling capacitor, two general - purpose diodes and a reservoir capacitor, a 5vdc voltage is generated which can be fed back into the vlcd pin of the 71m6511. the lcd drivers are enabled with the i/o register lcd_on ; i/o r egister lcd_fs is used to adjust contrast, and lcd_mode selects the operation mode (lcd type). downloaded from: http:///
71m6511/71m6511h single - phase energy meter ic data sheet november 20 10 page: 81 of 98 ? 2005 C 2010 teridian semiconductor corporation v2.7 a maxim integrated products brand lcd_bsten segments 71m6511 5v lcd commons vlcd v3p3 5vdc vdrv v3p3 lcd_fs lcd_en lcd_mode contrast on/off lcd type lcd_bsten segments 71m6511 5v lcd commons vlcd v3p3 5vdc vdrv v3p3 lcd_fs lcd_en lcd_mode contrast on/off lcd type figure 32 : lcd boost circuit downloaded from: http:///
71m6511/71m6511h single - phase energy meter ic data sheet november 20 10 page: 82 of 98 ? 2005 C 2010 teridian semiconductor corporation v2.7 a maxim integrated products brand connecting i2c eeproms i2c eeproms or other i2c compatible devices should be connected to the dio pi ns dio4 and dio5, as shown in figure 33 . pull - up resistors of roughly 3k ? to v3p3 should be used for both scl and sda signals. the dio_eex register in i/o ram must be set to 1 in order to convert the dio pins dio4 and dio5 to i2c pi ns scl and sda. dio4 dio5 71m6511 eeprom scl sda v3p3 3k 3k dio4 dio5 71m6511 eeprom scl sda v3p3 3k 3k figure 33 : eeprom connection connecting 5v devices in general, all pins of the 71m6511 are compatible with external 5v de vices. the exceptions are the power supply pins and the rx pin of the uart (see section elec trical specifications). 71m651x v in rx r1 = 100k ? v3p3 figure 34 : interfacing rx to a 0 - 5v signal figure 34 shows how a 5v signal from an external device can be safely interf aced to the rx pin. downloaded from: http:///
71m6511/71m6511h single - phase energy meter ic data sheet november 20 10 page: 83 of 98 ? 2005 C 2010 teridian semiconductor corporation v2.7 a maxim integrated products brand optical interface the pins opt_tx and opt_rx can be used for a regular serial interface, e.g. by connecti ng a rs_232 transceiver, or they can be used to directly operate optical components, e.g. an infrared diode and phototransistor implementing a flag interface. figure 35 shows the basic connections. the opt_tx pin becomes active when the i/o ram register opt_txdis is set to 0. opt_tx r 2 r 1 opt_rx 71m6511 v3p3 phototransistor led 100k 100pf v3p3 opt_tx r 2 r 1 opt_rx 71m6511 v3p3 phototransistor led 100k 100pf v3p3 figure 35 : connection for optical components connecting v1 and reset pins a voltage divider should be used to establish a safe range for v1 when the meter is in mission mode (v1 must be lower than 2.9v in all cases in order to keep the hardware watchdog timer enabled). for proper debugging or loading code into the 71m6511 mounted on a pcb, it is necessary to have a provision like the head er shown above r1 in figure 36 . a shorting jumper on this header pulls v1 up to v3p3, disabling the hardware watc hdog timer. c1 helps suppressing esd. v in r 2 v1 r 1 r 3 10k c 1 100pf v in r 2 v1 r 1 r 3 10k c 1 100pf figure 36 : voltage divider for v1 even though a functional meter will not necessarily need a reset swi tch, it is useful to have a reset pushbutton for prototyp ing. when a circuit is used in an emi environment, the resetz pin should be supported by the external components shown in figure 37 . r 1 should be in the range of 200 ? , r 2 should be around 10 ? . the capacitor c 1 should be 1nf. r1 and c1 should be mounted as close as possible to the ic. in cases where the trace from the pushbut ton switch to the resetz pin pos es a problem, r 2 can be removed. downloaded from: http:///
71m6511/71m6511h single - phase energy meter ic data sheet november 20 10 page: 84 of 98 ? 2005 C 2010 teridian semiconductor corporation v2.7 a maxim integrated products brand r 1 resetz 71m6511 dgnd v3p3 r 2 v3p3 pushbutton c 1 200 1nf 10 r 1 resetz 71m6511 dgnd v3p3 r 2 v3p3 pushbutton c 1 200 1nf 10 figure 37 : external components for resetz flash programming operational or test code can be programmed into the flash memory using either an in - circuit emulator or the flash download board module (fdbm) available from teridian. the flash programming procedure uses the e_rts, e_rxtx, and e_tclk pins. mpu firmware library all application - specific mpu functions mentioned above under application information are availab le from teridian as a standard ansi c library and as ansi c source code. the code is available as part of the demonstration kit for the 71m6511 and 71m6511h ics. the demonstration kits come with the 71m6511 or 71m6511h ic pr eprogrammed with demo firmware mounted on a functional samp le meter pcb (demo board). the demo boards allow for quick and efficient evaluation of the ic without having to write firmware or having to supply an in - circuit emulator (ice). a reference guide for firmware development on the 71m6511 and 71m6511h is available as a separ ate do cument (software users guide, sug). the users manuals supplied with the dem o kits contain mpu address maps for the demo code as well as other useful information, such as sample calibration procedures. downloaded from: http:///
71m6511/71m6511h single - phase energy meter ic data sheet november 20 10 page: 85 of 98 ? 2005 C 2010 teridian semiconductor corporation v2.7 a maxim integrated products brand specifications electrical s pecifications absolute maximum ratings supplies and ground pins: v3p3d, v3p3a ? 0.5v to 4.6v | v3p3d - v3p3a | 0v to 0.5v vlcd - 0.5v to 7v vbat - 0.5v to 4.6v gndd - 0.5v to +0.5v analog output pins: vref, vbias - 1ma to 1ma, - 0.5 to v3p3a+0 .5v v2p5 - 1ma to 1ma, - 0.5v to 3.0v analog input pins: ia, va, ib - 0.5v to v3p3a+0.5v xin, xout - 0.5v to 3.0v rx - 0.5v to 3.6v opt_rx - 1ma to 1ma - 0.5 to v3p3a+0.5v digital input pins: dio4 - 11, dio14 - 17, e_rxtx, e_rst - 0.5 to 6v test, re setz - 0.5 to v3p3d+0.5v all other pins: input pins - 5ma to 5ma - 0.5v to v3p3d+0.5v output pins - 30ma to 30ma - 0.5 to v3p3d+0.5v temperature: operating junction temperature (peak, 100ms) 140 c operating junction temperature (continuous) 125 c s torage temperature ? 45 c to 165 c solder temperature C 10 second duration 250 c esd stress: pins ia, va, ib, rx, tx, e_rst, e_tclk, e_rxtx 6kv all other pins 2kv stresses beyond absolute maximum ratings may cause permanent damage to th e device. these are stress ratings only and functional operation at these or any other conditions beyond those indicated under recomm ended operating conditions is not implied. exposure to absolute - maximum - rated conditions for extended periods may affect device relia bility. all voltages are with respect to gnda. downloaded from: http:///
71m6511/71m6511h single - phase energy meter ic data sheet november 20 10 page: 86 of 98 ? 2005 C 2010 teridian semiconductor corporation v2.7 a maxim integrated products brand recommended operating conditions parameter condition min typ max unit 3.3v supply voltage ( v3p3a, v3p3d ) ? normal operation 3.0 3.3 3.6 v battery backup 0 3.45 v vlcd 2.9 5.5 v vbat no battery extern ally connect to v3p3d battery backup 2.0 3.8 v operating temperature - 40 85 oc ? v3p3a and v3p3d should be shorted together on the circuit board. gnda and gndd should also be shorted on the circuit board. logic levels parameter condition min typ max unit digital high - level input voltage, v ih 2 v3p3d v digital low - level input voltage, v il ? 0.3 0.8 v digital high - level output voltage v oh i load = 1ma v3p3d C 0.4 v3p3d v i load = 15ma v3p3d - 0.6 1 v digital low - level output voltage v ol i load = 1 ma 0 0.4 v i load = 15ma 0.8 1 v input pull - up current, i il resetz e_rxtx, e_rst other digital inputs vin=0v 10 10 -1 100 100 1 a a a input pull down current, i ih test other digital inputs vin=v3p3d 10 -1 100 1 a a 1 guaranteed by d esign, not subject to test. downloaded from: http:///
71m6511/71m6511h single - phase energy meter ic data sheet november 20 10 page: 87 of 98 ? 2005 C 2010 teridian semiconductor corporation v2.7 a maxim integrated products brand supply current parameter condition min typ max unit v3p3a + v3p3d + vlcd current normal operation, v3p3a=v3p3d = vlcd =3.3v ckmpu=614khz vbat=3.6v no f lash memory write 6.4 9.5 ma v3p3a current 3.7 4.3 ma v3p3d current 2.5 4.8 ma vlcd current 0.2 0.4 ma vbat current - 300 300 na v3p3d current normal operation, v3p3a=v3p3d = vlcd =3.3v vbat=3.6v, no f lash memory write ckmpu=1,228khz ckmpu=2,456khz ckmpu=4,912khz 2.9 3.6 5.1 ma ma ma v3p3a + v3p3d current po wer save/sleep mode v3p3a=v3p3d = vlcd =3.3v, ce, adc, e_tclk, vref dis - abled ckmpu=153.5khz ckmpu=38.4khz 6 4.9 7 ma ma v3p3d current, write flash normal operation as above, except write f lash at ma xim um rate. 7 ma vbat current, vbat =3.6v battery backup, 25c v3p3a=v3p3d = vlcd =0v f osc = 32khz 85c 2 4 a 4 1 12 1 a 1 guaranteed by design, not subject to test. 2.5v voltage regulator unless otherwise specified, load = 5ma parameter condition min typ max unit voltage overhead v3p3 - v2p5 reduce v3p3 until v2p5 drops 200mv 440 mv pssr ? v2p5/ ? v3p3 rese tz =1, iload =0 -3 +3 mv/v downloaded from: http:///
71m6511/71m6511h single - phase energy meter ic data sheet november 20 10 page: 88 of 98 ? 2005 C 2010 teridian semiconductor corporation v2.7 a maxim integrated products brand vref, vbias unless otherwise specified, vref_dis =0 parameter condition min typ max unit vref output voltage, vnom(25) ta = 22oc 1.193 1.195 1.197 v vref chop step 40 mv vref output impedance vref_cal = 1, i load = 10a, -1 0a 2.5 k vnom definition a vnom(t) = vref(22) + (t C 22)tc1 + (t C 22) 2 tc2 v -- if trimbga and trimbgb available ( 6511h ) -- vref temperature coefficients tc1 (linear) tc2 (quadratic) trimbga, trimbgb, trimm[2:0]: see trimsel , trim registers x(33 -0 .28y) + 0.33y + 7.9 x(0.02 - 0.0002y) C 0.46 where x = 0.1trimbgb - 0.14(trimm[2:0]+0.5), 900 370000 _ 500 7404 .4 _ ? ? = bga trim nom temp y v/c v/c 2 vref(t) deviation from vnom(t) )40|,22 max(| 10 )( )( 6 ? ? t vnom t vnom t vref - 10 10 ppm/oc -- if trimbga and trimbgb not available ( 6511 ) -- vref t emperature coefficients tc1 (linear) tc2 (quadratic) 7.0 - 0.341 v/oc v/c 2 vref(t) deviation from vnom(t) )40|,22 max(| 10 )( )( 6 ? ? t vnom t vnom t vref ta = - 40oc to +85oc - 40 1 +40 1 ppm/oc vref aging ta = 25oc 25 ppm/ year vbias output voltage ta = 25 oc ta = - 40oc to 85oc (- 1%) (- 2%) 1 1.5 1.5 1 (+1%) (+2%) 1 v v vbias output impedance i load = 1ma, - 1ma 240 500 1 guaranteed by design, not subject to test. a this relationship describes the nominal behavior of vref at differe nt temperatures. crystal o scillator crystal is disconnected. test load is series 200pf, 100k ? connected between dgnd and xout. parameter condition min typ max unit maximum output power to crystal 4 crystal connected 1 w xin to xout capacitance 3 pf capacitance to dgnd xin xout 5 5 pf pf watchdog rtc_ok threshold 25 khz downloaded from: http:///
71m6511/71m6511h single - phase energy meter ic data sheet november 20 10 page: 89 of 98 ? 2005 C 2010 teridian semiconductor corporation v2.7 a maxim integrated products brand adc converter, vdd referenced fir_len =0, vref_dis =0, vddrefz =0 parameter condition min typ max unit recommended input range (vin - v3p3a ) - 250 250 mv peak voltage to current cross talk: ) cos( * 10 6 vcrosstalk vin vin vcrosstalk ? vin = 200mv peak, 65hz, on va vcrosstalk = largest measurement on ia or ib - 10 1 10 1 v/v thd (first 10 harmonics) 250mv - peak 20mv - peak vin=65hz, 64kpts fft, blackman - harris window - 75 - 90 db db input impedance vin=65hz 40 90 k temperature coefficient of input impedance vin=65hz 1.7 /c lsb size fir_len =1 150 nv/lsb digital full scale 2097152 lsb adc gain error versus %power supply variation 3.3/ 3 3 100 / 357 10 6 a p v v nv nout in pk ? ? vin=200mv peak, 65hz v3p3a=3.0v, 3.6v 50 ppm/% input offset (vin - v3p3a ) - 10 10 mv 1 guaranteed by design, not subject to test. optic al interface parameter condition min typ max unit opt_tx v oh ( v3p3d - opt_tx ) i source =1ma 0.4 v opt_tx v ol i sink =20ma 0.7 v opt_rx vin threshold (vin rising +vin falling )/2 200 250 300 mv opt_rx vin hysteresis (vin rising - vin falling ) 5 30 mv opt_rx input impedance |vin| 300mv 1 m temperature sensor parameter condition min typ max unit nominal sensitivity (s n ) 2 t a =25oc, t a =75oc nominal relationship: n(t)= s n *t+n n - 900 lsb/oc nominal offset (n n ) 2 400000 lsb temperatu re error 1 n s n tn t err ))25( )(( )25 ( ? ? ? = t a = - 40oc to +85oc -3 1 3 1 oc 1 guaranteed by design, not subject to test. 2 this parameter defines a nominal relationship rather than a measured paramet er. correct circuit operation is verified with ot her specs that use this nominal relationship as a reference. downloaded from: http:///
71m6511/71m6511h single - phase energy meter ic data sheet november 20 10 page: 90 of 98 ? 2005 C 2010 teridian semiconductor corporation v2.7 a maxim integrated products brand lcd boost parameter condition min typ max unit vdrv frequency osc/2 hz vdrv sink current vol=1.5v 1.2 2.75 ma vdrv source current voh=1.5v 1.2 2.6 ma vlcd target voltage 4.5 5.5 v vlcd input current vlcd=5.0v, lcd_fs =1f, lcd_mode =0,1,2,3 lcd_bsten =1 450 a lcd drivers applies to all com and seg pins. unless otherwise stated, vlcd= 5.0v, lcd_fs =1f parameter condition min typ max unit vlc0 max voltage ( lcd_fs =1f) with respect to vlcd - 0.2 0 v vl c0 min voltage ( lcd_fs =00) with respect to vlcd*0.7 - 0.2 0.2 v vlc1 voltage, 1/3 bias ? bias with respect to 2*vlcd/3 with respect to vlcd/2 - 10 - 10 +10 +10 % % vlc0 voltage, 1/3 bias ? bias with respect to vlcd/3 with respect to vlcd/2 -15 - 10 +15 +10 % % output impedance ? i load =10a 30 k rtc parameter condition min typ max unit range for date 2000 - 2255 year resetz parameter condition min typ max unit reset pulse width 5 s reset pulse fall time 1 1 s 1 guaranteed by design, not subject to test. comparators parameter condition min typ max unit offset voltage v1 - vbias - 20 15 mv hysteresis current v1 vin = vbias - 100mv 0.8 1.2 a response time v1 + 100mv overdrive 2 15 s wd disable threshold ( v1 - v3p3a ) - 400 - 10 mv downloaded from: http:///
71m6511/71m6511h single - phase energy meter ic data sheet november 20 10 page: 91 of 98 ? 2005 C 2010 teridian semiconductor corporation v2.7 a maxim integrated products brand ram and flash memory parameter condition min typ max unit ce ram wait states ckmpu = 4.9mhz 5 cycles ckmpu = 1.25mhz 2 cycles flash write cycles - 40c to +85c 20,000 cycles flash data retention 85c 10 years flash data retention 25c 100 years flash byte writes between page or mass erase operations 2 cycles flash memory timing parameter condition min typ max unit write time per byte 42 s page erase (512 bytes) 20 ms mass erase 200 ms flash byte writes between page or mass erase operations 2 cycles eeprom interface parameter condition min typ max unit write clock frequency ckmpu=4.9mhz, using interrupts 78 khz ckmpu=4.9mhz, bit - banging dio4/5 150 khz recommended external components name from to function value unit c1 v3p3a agnd bypass capacitor for 3.3v supply 0.1 20% f c2 v3p3d dgnd bypass capacitor for 3.3v supply 0.1 20% f xtal xin xout 32.768khz crystal. electrically similar to ecs ecx - 3ta series 32.768 khz cxs xin agnd load capacitor for crystal (depends on crystal specs and board par asitics). 22 10% pf cxl xout agnd 22 10% pf cbias vbias agnd bypass capacitor for vbias 1000 20% pf cbst1 vdrv external boost charging capacitor 33 20% nf c2p5 v2p5 dgnd bypass capacitor for v2p5 0.1 20% f cbst2 vlcd dgnd boost bypass capacitor 0 .22 20% f downloaded from: http:///
71m6511/71m6511h single - phase energy meter ic data sheet november 20 10 page: 92 of 98 ? 2005 C 2010 teridian semiconductor corporation v2.7 a maxim integrated products brand packaging information 64 - pin lqfp package outline (bottom view). note: controlling dimensions are in mm . 11.7 12.3 0.60 typ. 1.40 1.60 11.7 12.3 0.00 0.20 9.8 10.2 0.50 typ. 0.14 0.28 pin no. 1 indicator + downloaded from: http:///
71m6511/71m6511h single - phase energy meter ic data sheet november 20 10 page: 93 of 98 ? 2005 C 2010 teridian semiconductor corporation v2.7 a maxim integrated products brand pinout (top view) teridian 71m6511-igt gndd e_rxtx opt_tx tmuxout tx seg3/sclk vdrv cktest v3p3d seg4/ssdata seg5/sfr seg37/dio17 com1 com0 com2 33 64 resetz v2p5 vbat rx seg31/dio11 seg30/dio10 seg29/dio9 seg28/dio8 seg27/dio7 seg26/dio6 seg25/dio5 seg19 seg24/dio4 seg18 seg17 seg16 com3 seg0 seg35/dio15 seg36/dio16 seg6/srdy seg8 seg1 seg2 seg34/dio14 seg7/mux_sync seg12 seg10 seg11 seg9 seg15 seg13 seg14 e_tclk va opt_rx test gnda v3p3a e_rst vlcd xout v1 xin gnda ia vbias vref 1 17 23 4 5 67 8 9 1011 12 13 14 1516 1819 2021 22 24 2325 26 27 28 29 30 31 32 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 6362 61 6059 58 57 56 55 54 53 52 51 50 49 ib downloaded from: http:///
71m6511/71m6511h single - phase energy meter ic data sheet november 20 10 page: 94 of 98 ? 2005 C 2010 teridian semiconductor corporation v2.7 a maxim integrated products brand pin descriptions power/ground pins name pin # type desc ription gnda 49, 58 p analog ground: this pin should be connected directly to the ground plane . gndd 1 p digital ground: this pin should be connected directly to the ground plane. v3p3a 50 p analog power supply: a 3.3v power supply should be connecte d to this pin. v3p3d 9 p digital power supply: a 3.3v power supply should be connected to this pi n. vbat 46 p battery backup power supply. a battery or super - capacitor should be connected between vbat and gndd. if no battery is used, connect vbat to v3p 3d. v2p5 47 o output of the internal 2.5v regulator. a 0.1f capacitor to gnda shou ld be connected to this pin. vlcd 62 p lcd power supply. a dc source of 3.3v to 5.0v should be connected to this pin. analog pins name pin # type circuit description ia 54 i 6 line current sense input: this pin is a voltage input to the inte rnal a/d converter. typically, it is connected to the output of a current transformer or shunt resistor. if the pin is unused it must be connected to v3p3a or tied to the i b pin. va 51 i 6 line voltage sense input: this pin is a voltage input to the interna l a/d converter. typically, it is connected to the output of a resistor divider. if the pin is unused it must be tied to v3p3a. ib 53 i 6 line current sense input: this pin is a voltage input to the internal a/d converter. typically, it is connected to the output of a current transformer or shunt resistor. if the pin is unused it must be connected to v3p3a or tied to the i a pin. v1 56 i 7 comparator input: this pin is a voltage i nput to the internal comparator. the voltage applied to the pin is compared to an internal reference voltage of 1. 5v. if the input voltage is above the reference, the comparator output will be high (1). if the comparator output is low, a voltage fault will occur. see the pre cau tions in the applications section for terminating this pin. vref 55 o 9 voltage reference for the adc. a 0.1f capacitor to gnda should be connected to this pin. vbias 52 o 9 this pin outputs the reference voltage used by the powe r fault detection circuit. a 1,000pf capacitor to gnd should be connected to this pin. xin xout 59 61 i 8 crystal inputs: a 32khz style crystal should be connected across these pins. typically, a 20pf capacitor is also connected from each pin to gnd a. it is important to minimize the capacitance between these pins. see the crystal manufacturer datasheet for details. vdrv 7 o 4 voltage boost output. pin types: p = power, o = output, i = input, i/o = input/outp ut the circuit number denotes the equivalent circuit, as specified unde r i/o equivalent circuits. downloaded from: http:///
71m6511/71m6511h single - phase energy meter ic data sheet november 20 10 page: 95 of 98 ? 2005 C 2010 teridian semiconductor corporation v2.7 a maxim integrated products brand digital pins: name pin # type circuit description com3, com2, com1, com0 16 15 14 13 o 5 lcd common outputs: these 4 pins provide the select signals for the lcd display. seg19seg8, seg2seg0 see pinout o 5 dedicated lcd segment output pins. seg24/dio4 seg31/dio11, seg34/dio14 seg37/dio17 see pinout o 3, 4, 5 multi - use pins, configurable as either lcd seg driver or dio (dio4 = sck, dio5 = sda when configu red as eeprom interface, wpulse = dio6, varpulse = dio7 when configured as pulse outputs). if unused, these pins must be configured as outputs. seg7/ mux_sync 24 o 4, 5 multi - use - pin lcd segment output/ mux_sync is output for synchronous serial interface seg6/srdy 23 i/o 2, 5 multi - use - pin, lcd segment outputs/ srdy input for synchronous serial interface. when configured as srdy, this pin must be pulled down to gndd. seg5/sfr 11 o 4, 5 multi - use - pin, lcd segment output/ sfr output for synchronous serial interface. seg4/sdata 10 o 4, 5 multi - use - pin, lcd segment output/ sdata output for synchronous serial interface. seg3/sclk 6 o 4, 5 multi - use - pin, lcd segment output/ sclk output for synchronous serial interface. cktest 8 o 4 clock pll output. can be e nabled and disabled by ckout_dis . tmuxout 4 o 4 digital output test multiplexer. controlled by dmux[3:0]. opt_rx 57 i 7 optical receive input: this pin may receive a signal from an ex ternal photo - detector used in an ir serial interface. if this pin is un used it must be terminated to v3p3d or gndd. opt_tx 3 o 4 optical led transmit output: this pin is designed to directly dr ive an led for transmitting data in an ir serial interface. can be tri stated with opt_txdis to be multiplexed with other dio pins. r esetz 48 i 1 this input pin resets the chip into a known state. for normal oper ation, this pin is set to 1. to reset the chip, this pin is driven to 0. this pin has an internal 30a (nominal) current source pull up. a 0.1f ca - pacitor to gndd should be connected to this pin. see the pre cau - tions in the applications section for terminating this pin. rx 45 i 3 uart input. th e voltage applied at this input must be below 3.6v. if this pin is unused it must be terminated to v3p3d or gnd d. tx 5 o 4 uart output. e_rxtx 2 i/o 1, 4 emulator serial data. this pin has an internal pull - up resistor. e_tclk 64 o 4 emulator clock. e_rst 63 i/o 1, 4 emulator reset. this pin has an internal pull - up resistor. see the precautions in the applications section for terminating this pin. test 60 i 7 enables production test. this pin must be grounded in normal operation. pin types: p = power, o = output, i = input, i/o = input/output the circuit number denotes the equivalent circuit, as specified on the following page. downloaded from: http:///
71m6511/71m6511h single - phase energy meter ic data sheet november 20 10 page: 96 of 98 ? 2005 C 2010 teridian semiconductor corporation v2.7 a maxim integrated products brand i/o equivalent circuits: oscillator equivalent circuit type 8: oscillator i/o digital input equivalent circuit type 1: standard digital input or pin configured as dio input with internal pull-up gndd 110k v3p3d cmos input v3p3d digital input pin digital input type 2: pin configured as dio input with internal pull-down gndd 110k gndd cmos input v3p3d digital input pin digital input type 3: standard digital input or pin configured as dio input gndd cmos input v3p3d digital input pin cmos output gndd v3p3d gndd v3p3d digital output equivalent circuit type 4: standard digital output or pin configured as dio output digital output pin lcd output equivalent circuit type 5: lcd seg or pin configured as lcd seg lcd driver gndd lcd seg output pin to mux gnda v3p3a analog input equivalent circuit type 6 : adc input analog input pin comparator input equivalent circuit type 7: comparator input gnda v3p3a to comparator comparator input pin to oscillator gndd v3p3d oscillator pin vref equivalent circuit type 9: vref from internal reference gnda v3p3a vref pin v2p5 equivalent circuit type 10: v2p5 from internal reference gndd v3p3d v2p5 pin vlcd equivalent circuit type 11: vlcd power gndd lcd drivers vlcd pin vbat equivalent circuit type 12: vbat power gndd power down circuits vbat pin downloaded from: http:///
71m6511/71m6511h single - phase energy meter ic data sheet november 20 10 page: 97 of 98 ? 2005 C 2010 teridian semiconductor corporation v2.7 a maxim integrated products brand ordering information part description ordering number package marking 71m6511 64 - pin lqfp, 0.5% a ccuracy 71m6511 - igt 71m6511 - igt 71m6511 64 - pin lead - free lqfp, 0.5% accuracy 71m6511 - igt/f 71m6511 - igt 71m6511 64 - pin lqfp, 0.5% accuracy, t&r 71m6511 - igtr 71m6511 - igt 71m6511 64 - pin lead - free lqfp, 0.5% accuracy, t&r 71m6511 - igtr/f 71m6511 - igt 71m6511 h 64 - pin lqfp, 0.1% accuracy 71m6511h - igt 71m6511h - igt 71m6511h 64 - pin lead - free lqfp, 0.1% accuracy 71m6511h - igt/f 71m6511h - igt 71m6511h 64 - pin lqfp, 0.1% accuracy, t&r 71m6511h - igtr 71m6511h - igt 71m6511h 64 - pin lead - free lqfp, 0.1% accuracy, t&r 71m6511h - igtr/f 71m6511h - igt downloaded from: http:///
71m6511/71m6511h single - phase energy meter ic data sheet november 20 10 maxim cannot assume responsibility for use of any circuitry other than ci rcuitry entirely embodied in a maxim product. no c ircuit patent licenses are implied. maxim reserves the right to change the circuitry and sp ecifications without notice at any time. maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408 - 737 - 7600 ? 2010 maxim integrated products maxim is a registered trademark of maxim integrated products. a maxim integrated products brand revision history revision date description 2.7 11/ 10 added guaranteed by design specifications to the electrical specifications downloaded from: http:///

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